OpenRISC also has divide overflow exception and integer overflow exceptions. Both are generally avoidably with the "exception with code" instruction, some littl

OpenRISC also has divide overflow exception and integer overflow exceptions. Both are generally avoidably with the "exception with code" instruction, some little condition checking and some small compiler work. MIPS, for instance, does not have divide overflow exception. It uses compare, conditional branching and "exception with exception code" instruction. Most of the time (int32_t/int32_t) division is safe, because divisor is checked for zero in the code logic somewhere else and guaranteed to be non-zero. Sometimes (int64_t/int32_t) it is not safe (higher word is divident can be bigger than divisor) and checking code must be executed in run time. And execution overhead is so little that it is quite good design choice. You don't have hardware that drains energy constantly for slight slowdown for code that is rare. As far I can remember, RISC-V does not have divide overflow exception. As a rule of thumb: if you can put something into software, please do (overflow checks, code scheduling instead of delay slots). Hardware is for things where software can't help (branch prefetch, out of order, etc).