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SiFive Announces First RISC-V OoO CPU Core
- fulafel 7y ago"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.
- wolf550e 7y agoIP cores are sometimes deployed on FPGAs though, so that can be a working chip (depending on definitions).
- gnode 7y agoI think this may be more than a register-level transfer abstraction. The slides make claims about die area and frequency, and show a layout. SiFive offer IP but also produce SoCs (presumably with TSMC, SMIC, and GlobalFoundries, who are listed as partners).
- cfallin 7y ago"IP core" can mean "soft IP", which is just RTL, or "hard IP", which is a full layout (set of mask layers), ready to put on silicon. I haven't read the SiFive announcement closely, but if they're quoting area/frequency/power numbers, it would most likely be the latter.
- gnode 7y agoInterestingly, although all the RTL for the SiFive Freedom platform is in the SiFive's GitHub repository, and they've produced chips and boards (with public schematics and BOM), the hard IP doesn't appear to be public. I wonder if this is because the hard IP is specific to the fabs' trade secret tooling, and so subject to their NDAs, making it impossible to distribute publicly.
- monocasa 7y agoYou're on point with the second paragraph. I only know of one chip fab that has it's design rules public, and they're an open source fab running out of HKUST that'll give you about Arduino level gate counts.
- wolf550e 7y agoWhy can't a fab with something like 28nm use public design rules? I guess there aren't valuable trade secrets still in a process that old. But some chips can usably be made on such a process.
- Sanzig 7y agoThere's a lot of mixed-signal specialty ASICs at the 350 nm and 180 nm nodes. As long as you don't need the density, it's a great option. Masks are relatively cheap and the processes are dialed in extremely well at this point. Just because the tech is 20-30 years old doesn't mean it's not useful.
- monocasa 7y agoThere's absolutely valuable trade secrets even at 28nm. For starters, a fab's work at 28nm would absolutely inform descions on newer nodes. Additionally, the older nodes don't just shut down their lines, but are dependent on continued use to pay off their massive capital investment. They're still competing with the other 28nm fabs.
- namibj 7y agoI wish one of them would just try and release a 180nm process in a way that allows public domain maskset distribution. If it flops, so be it; if not, many people like myself can suddenly start hacking on analog or mixed IC designs for potentially exotic things, like analog-computer-based UAV controllers that integrate the control loop with e.g. external feedback like simple doppler/chirp radar to reach microseconds of feedback latency and thus enabling monolithic closed-loop control. A miniaturized version of https://www.research-drone.com/en/ https://www.research-drone.com/en/ with the blade's counterweight being a single neodymium magnet in an outrunner configuration and a ferrite stator fabricated using SMD inductor technology to target the 5g (+ payload + battery) UAV class would be interesting, but the ~3KHz (typical disc loading and high subsonic tip speed) rotation rate (~200k rpm) make software control of the motor driver difficult.
- _chris_ 7y agoWhen you are selling IP like this you would need to do your own physical design due diligence, even if the deliverable is just some Verilog code.
- AWildC182 7y agoGod I hate that term. It's not your secret sauce intellectual property, it's a fucking library. Possibly the biggest reason FPGA/ASIC tech has lagged so hard behind CPU/GPGPU in terms of consumer use is because they have managed to use their hardware to completely stifle all open source software (they even go to some lengths to distance themselves from the term "software"). FPGA libraries are almost always encrypted and have to be treated as a true black box when designing. Doing things as mundane as interacting with a PCIe bus or simple signal filtering are all locked away behind ludicrously overpriced "IP" packages that are often vendor specific.
- zozbot234 7y agoInteracting with a PCIe bus does not seem "mundane" to me. Analog electronics is hard, and, just as importantly, process-specific (and the details of any one process are generally kept strictly confidential to the fab, with tightly-binding NDAs). Now, when it comes to pure digital logic I agree, but that's also where open hardware (with meaningful contributions by SiFive themselves) has been most successful.
- temac 7y agoThe analog parts of PCIe interfaces are not programmable. The artificially black boxes we are talking about are purely digital. They use fixed resources but we are not asking for the design of those parts.
- fwip 7y agoWhy can't a library be IP?
- temac 7y agoIP means nothing. It's a poorly defined conglomerate of vastly different laws, like about brands, patents, models, etc. A library is typically "protected" (that is: artificially restricted) by copyright, and the situation is then blurry but in some cases also patents (depending on the region of the world and/or good lawyers knowing the magic words to patent non-patentable things) and trade secrets.
- jagger27 7y ago> A lot of the performance increases of the U8-series come thanks to the increased frequencies capabilities which are 1.4x higher this generation, with the core scaling up to 2.6GHz on 7nm. Pretty cool that these chips are approaching performance parity so quickly.
- baybal2 7y ago> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio. Where does SiFive get such an expertise in size optimisation?
- wmf 7y agoI wonder if that's comparing the non-vector U84 against the A72 with Neon.
- brucehoult 7y agoIt will be, yes, and the U87 with a vector unit will obviously be a bit bigger. There are many applications where a vector unit is unnecessary silicon that adds nothing but cost and power consumption.
- audunw 7y agoThe RISC-V ISA was made with some hindsight of what choices makes it easy to optimize for OoO superscalar CPUs. If I remember correctly, that's one of the reasons everyone jumped ship from OpenRISC to RISC-V (the big mistake in OpenRISC being branch delay slots I believe) It might also help starting from scratch. I'm also not convinced it's entirely an apples-to-apples comparison. ARM might support more complex instructions that their core don't, and the ARM core might have features like TrustZone.
- cesarb 7y ago> The RISC-V ISA was made with some hindsight of what choices makes it easy to optimize for OoO superscalar CPUs. ARM's 64-bit architecture (AArch64) was also made with similar hindsight, so that's probably not the whole reason.
- 7y ago
- bcheung 7y agoI wasn't sure what OoO stood for and since they never mentioned it in the article I had to look it up. For anyone else who is asking the same question. OoO = out of order execution
- BookPage 7y agoIt’s actually mentioned in a header after the third paragraph in the article...
- bcheung 7y agoYeah, I saw that later on when I continued reading. I did a Find on the page and was looking for "ooo" and didn't find anything like "order of order (ooo)" because it's customary to define it when it is first used.
- SlowRobotAhead 7y agoI’m right there with you! I’ve been doing embedded hardware and CE work for 15 years non-stop, and had no idea what OoO meant. Kept thinking “on a”. As in SoC or PoC.
- yhvh 7y agoIs there a risc-v chip on the market which includes Bluetooth?
- arcticbull 7y agoUsually Bluetooth modules are add-on peripherals, unless I'm mistaken.
- childintime 7y agoEspressif is planning a RISCV based ESP32 upgrade, it'll probably will have Bluetooth. No schedule yet.
- Shtirlic 7y agoSiFive HiFive1 Rev B with esp32(WiFi/BT (off-chip))
- yhvh 7y agoYeah I know about this, I need it all in one package.
- mattnewport 7y agoA Raspberry Pi type SBC based on this would be neat, is that something we can expect to see any time soon in light of this announcement or is that not an application this is really aimed at?
- snvzz 7y agoThis is most likely to come from lowrisc[0] instead. [0] https://www.lowrisc.org/ https://www.lowrisc.org/
- brucehoult 7y agoThat would be neat, and would come out somewhere similar to a Pi 4 (which are pretty awesome). Note that the Pi 4 has ARM processor cores, but ARM doesn't make either the processor chip or the board. Broadcom design and make the BCM2711 SoC, and the Raspberry Pi Foundation designed and manufactures the board. No doubt SiFive would be very happy to work with someone who wanted to make retail SoCs and/or SBCs using the U84, but as with ARM it's not really their business model to do that themselves. SiFive has made several low-volume chips and boards for potential core IP customers to use for evaluation and development e.g. the $999 HiFive Unleashed. ARM similarly offers a $10000 dev board for the A72.
- monocasa 7y agoHave we gotten confirmation yet on whether this is a BOOM core or not? It certainly feels like it is