Lakefield is a 1+4 core part, it's tiny and won't need chiplets. Chiplets are necessary only once you get to core counts that won't fit on a single square of si

Lakefield is a 1+4 core part, it's tiny and won't need chiplets. Chiplets are necessary only once you get to core counts that won't fit on a single square of silicon. Intel have announced co-EMIB, which seems to be their solution to 2D integration of 3D-stacked parts. https://fuse.wikichip.org/news/2503/intel-introduces-co-emib-to-stitch-multiple-3d-die-stacks-together-adds-omni-directional-interconnects/ https://fuse.wikichip.org/news/2503/intel-introduces-co-emib...