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Signs currently point towards Intel skipping the chiplet-on-interposer model AMD is currently using and going directly to 3D stacking i.e. dies directly on top
by ATsch 7y ago
Signs currently point towards Intel skipping the chiplet-on-interposer model AMD is currently using and going directly to 3D stacking i.e. dies directly on top of other dies.
They did a paper launch of their "Foveros" 3D stacking technology and "Lakefield" Architecture this year, which is clearly still in very early stages, and also tellingly announced at their investor meetup. It will probably be some years before we see any real chips with this.
AMD is speculated to go with a combined model (chiplets, but stacked cache on the IO Die) with Zen 3/4 and then go full 3D for Zen 5 or so.
- Veedrac 7y agoThis conjecture sounds wrong to me. 3D stacking and chiplets are complementary; going only 3D has thermal and cost issues, so it makes sense to combine both. One shouldn't replace the other any time soon.
- ATsch 7y agoWell, the Lakefield design is fully 3D, and Intel has not announced any chiplet based designs, so either they made it all up, or they're convinced they can make it work in the next few years.
- Veedrac 7y agoLakefield is a 1+4 core part, it's tiny and won't need chiplets. Chiplets are necessary only once you get to core counts that won't fit on a single square of silicon. Intel have announced co-EMIB, which seems to be their solution to 2D integration of 3D-stacked parts. https://fuse.wikichip.org/news/2503/intel-introduces-co-emib-to-stitch-multiple-3d-die-stacks-together-adds-omni-directional-interconnects/ https://fuse.wikichip.org/news/2503/intel-introduces-co-emib...