The memory isnt trained -- the PHY is. Its PLL and signal adjustment -- not too dissimilar to how a cable modem "trains" to get settings right for your specific

The memory isnt trained -- the PHY is. Its PLL and signal adjustment -- not too dissimilar to how a cable modem "trains" to get settings right for your specific line's characteristics. PCs have codified it mostly to a set of well known and understood timings that are interchangable, so in that domain its easy. But raw DDR chips used with SOCs is much much harder because you're not beholden to Intel's standards for the PHY or the RAM.