Modern DDR PHYs require PLL training and adjustment to communicate to the RAM chips because DDR is runs at such high speeds that it is mostly operating in the a

Modern DDR PHYs require PLL training and adjustment to communicate to the RAM chips because DDR is runs at such high speeds that it is mostly operating in the analog domain these days. Often this is done by setting registers. The trick is that its hundreds of thousands of registers to alter the way the PHY behaves with regard to impedance and other parameters, and the vast majority are undocumented. So its done with a two stage thing: the first is a generative program that analyses the eye diagrams using feedback from the PHY over a long period of time to get the majority of the settings. The second half is actually getting the PHY PLLs to sync with the clocks and the RAM, which is done by the PHY at runtime, every boot.