I'm not a huge fan of chisel. I decided to give it a serious chance, allocated a few weeks to learn Scala and chisel and had some test projects to try it on.

I'm not a huge fan of chisel. I decided to give it a serious chance, allocated a few weeks to learn Scala and chisel and had some test projects to try it on. In the end I gave up not really having seen the benefits of chisel over systemverilog or even vhdl. The riscv design that was the posterchild of chisel efficiency was coded in pure verilog by someone who knew his trade and the verilog version looks so much cleaner. If I were to describe chisel in one word it would be "arrogance".