The term is "synthesis." You have a synthesis tool which turns your high level (verilog or whatever) hardware description into a netlist of gates and other hard

The term is "synthesis." You have a synthesis tool which turns your high level (verilog or whatever) hardware description into a netlist of gates and other hardware primitives. That's followed by "implementation," where the netlist is fed through the FPGA layout planner and place-and-route tool to generate a bitstream.