It's very easy to make a DDR interface in an FPGA, it's difficult to make it run at the mark speed... (but this observation is generic for all FPGA-stuff reall

It's very easy to make a DDR interface in an FPGA, it's difficult to make it run at the mark speed... (but this observation is generic for all FPGA-stuff really, it seems easy first, it's just another language etc.. but you need to learn timing analysis and constraints and optimization to use it for real)