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When a SWE really starts to understand how complex a modern DDR controller is at the silicon level, two things happen: 1. You start to wonder how very, very fa

When a SWE really starts to understand how complex a modern DDR controller is at the silicon level, two things happen: 1. You start to wonder how very, very far your code runs from the theoretical capabilities of the hardware and you start experiencing existential doubts. 2. You are overcome by a deep and immense feeling of gratitude towards whomever managed to force all that complexity to remain hidden underneath the simple memory abstraction your rely on to write day to day code.

tpmx 7y ago
Any links to reading materials for learning about that? Found this PDF from Samsung regarding the DDR4 interface itself: https://www.samsung.com/semiconductor/global.semi/file/resource/2017/11/DDR4_Device_Operations_Rev11_Oct_14-0.pdf https://www.samsung.com/semiconductor/global.semi/file/resou... (The JEDEC DDR4 spec is $284 to download...)
- lnsru 7y ago
  Start reading data sheets of memory chips. They have state diagrams. DDR2 is great technology to start with. Some random memory chip: https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr2/512mbddr2.pdf https://www.micron.com/-/media/client/global/documents/produ... on page 9 you have state diagram. There is simulation model available.
  - exikyut 7y ago
    Where is this simulation model, and (here's hoping) is it cross-platform? Also, is it anything like http://www.visual6502.org/JSSim/ http://www.visual6502.org/JSSim/?
    - lnsru 7y ago
      On Micron’s website for most of their parts. Worked very well with Alteras’s memory controller some time ago. I needed to evaluate read write throughput for specific read/write patterns before designing printed circuit boards. I don’t unterstand what you mean with cross-platform.
jacquesm 7y ago
I try really hard to not go down that particular rabbit hole as it will always end up being 100% sure that software can't possibly work reliably or even at all. The degree to which we assume that our hardware is able to move stuff from point 'a' to point 'b' at a couple of billion times per second is scary.
- nickpsecurity 7y ago
  Although I don't know hardware, I read lots of stuff about developing it to get a better idea. Among the more interesting reads were slides about each process shrink along with challenges they brought. Especially from beginning of Deep Sub-Micron toward 28nm. The impression I got, esp by 28nm, is the hardware is inherently broken in quite a few ways. They have to correct the masks with algorithms, they do image recognition on circuits to spot patterns that act up, extra latches, variance across the chip/wafer, aging effects... list goes on. Miracle they even work at all. These things are also why I only trust old nodes for security. Sort of.

tpmx 7y ago

Any links to reading materials for learning about that? Found this PDF from Samsung regarding the DDR4 interface itself: https://www.samsung.com/semiconductor/global.semi/file/resource/2017/11/DDR4_Device_Operations_Rev11_Oct_14-0.pdf https://www.samsung.com/semiconductor/global.semi/file/resou... (The JEDEC DDR4 spec is $284 to download...)

lnsru 7y ago
Start reading data sheets of memory chips. They have state diagrams. DDR2 is great technology to start with. Some random memory chip: https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr2/512mbddr2.pdf https://www.micron.com/-/media/client/global/documents/produ... on page 9 you have state diagram. There is simulation model available.
- exikyut 7y ago
  Where is this simulation model, and (here's hoping) is it cross-platform? Also, is it anything like http://www.visual6502.org/JSSim/ http://www.visual6502.org/JSSim/?
  - lnsru 7y ago
    On Micron’s website for most of their parts. Worked very well with Alteras’s memory controller some time ago. I needed to evaluate read write throughput for specific read/write patterns before designing printed circuit boards. I don’t unterstand what you mean with cross-platform.

jacquesm 7y ago

I try really hard to not go down that particular rabbit hole as it will always end up being 100% sure that software can't possibly work reliably or even at all. The degree to which we assume that our hardware is able to move stuff from point 'a' to point 'b' at a couple of billion times per second is scary.

nickpsecurity 7y ago
Although I don't know hardware, I read lots of stuff about developing it to get a better idea. Among the more interesting reads were slides about each process shrink along with challenges they brought. Especially from beginning of Deep Sub-Micron toward 28nm. The impression I got, esp by 28nm, is the hardware is inherently broken in quite a few ways. They have to correct the masks with algorithms, they do image recognition on circuits to spot patterns that act up, extra latches, variance across the chip/wafer, aging effects... list goes on. Miracle they even work at all. These things are also why I only trust old nodes for security. Sort of.