5 ms·
> From existing PolarFire FPGAs, Risc-V versions are inheriting security functions including: DPA-resistant bit-stream programming, anti-tamper, a cryptographic
by metaphor 7y ago
> From existing PolarFire FPGAs, Risc-V versions are inheriting security functions including: DPA-resistant bit-stream programming, anti-tamper, a cryptographical bound supply chain assurance, a physically un-clonable function, a true random number generator and a side-channel resistant crypto-coprocessor.
> In addition according to Microchip the processors will have secure boot (128kbyte boot flash), physical memory protection and, on all memories: single-bit error correction and double-bit error detection. THe firm is also claiming Spectre and Meltdown immunity.
With all this buzzword bingo, you'd think the company formerly known as Actel was actively marketing to a defense industry with selective amnesia[1].
[1] https://doi.org/10.1007/978-3-642-33027-8_2 https://doi.org/10.1007/978-3-642-33027-8_2
- asm_ 7y agoMicrosemi is the company formerly known as Actel. Microchip is the company that makes (amongst other things) PICs and bought Atmel (AVRs etc) edit: I see the article is the one in the wrong - it should have said Microsemi
- metaphor 7y agoThe article isn't wrong; you're acquisition history is simply miscalibrated. PolarFire is the operand signal...everything else is in the noise.
- asm_ 7y agoAh yes - I missed an extra acquisition! Microchip acquired Microsemi (who acquired Actel)! They are gobbling up everything now. FWIW - I quite like the Actel/Microsemi/Microchip FPGAs. Their ProASICs and Igloos have been solid for me.
- adwn 7y agoTheir software is utter crap, though – even by the standards of the EDA industry. Some of their tools (I'm looking at you, designer) are so old and unmaintained, that they still show the Actel logo.
- ncmncm 7y agoIs there no Free Software alternative for those devices?
- adwn 7y agoNo. Unlike mainstream CPUs, for which sufficient information is publicly available to develop competitive compilers, FPGAs are closed systems. There is enough documentation to write the synthesis and map steps (which compile VHDL/Verilog/whatever to an architecture dependent netlist) and for the place step (which assigns instances from the netlist to blocks on the FPGA device). For the remaining steps (routing, static timing analysis, and bitstream generation), hardly any required documentation is available. For a couple of small, outdated FPGAs, some of that information has been reverse-engineered and used for open source software, but I don't know how reliable, e.g., their static timing analysis is. I would never, ever use that for a non-hobby project.