Right, but these are simulators, while the article is looking for a language to both simulate and synthesize using open source tooling. Yosys (which AFAIK is s

Right, but these are simulators, while the article is looking for a language to both simulate and synthesize using open source tooling. Yosys (which AFAIK is still the only non-toy open source synthesis tool) supports a _very_ small subset of SV, and does not support VHDL (at least in the open source version).