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FPGA Design for Software Engineers
- inamberclad 7y agoI'm surprised that no one has brought up the Lattice IceStick. It's an oversized USB stick with an ice40 FPGA on it and it's the cheapest option I've seen.
- srjilarious 7y agoThe IceStick is also nice and a bit cheaper at ~$25 but it has a smaller 1k logic element Ice40 FPGA on it whereas the TinyFPGA-BX has a larger 8k logic element FPGA.
- tverbeure 7y agoThe cheapest options with much larger amount of logic are: Upduino v2.1 ($20) and the never dying EP2C5T144 board ($10). The latter requires a USB blaster dongle to program things so the Upduino has the upper hand IMO, especially because it also has very lightweight open source tools.
- sideshowmel 7y agoI've been looking for something like this for a while. It's hard to break into FPGA design coming from a Software Engineering viewpoint, but I think it teaches how the machine REALLY works and can produce better Software developers.
- danharaj 7y agoI found Digital Design by Mano and Ciletti to be a nice introduction to the basic building blocks of digital circuits. Four weeks later I'm studying laplace transforms and transfer functions please send help.
- deleted 7y ago[deleted]
- rrss 7y agoGood on you, every idiot can count to one. https://en.wikipedia.org/wiki/Bob_Widlar#Fairchild_Semiconductor_(1963%E2%80%931965) https://en.wikipedia.org/wiki/Bob_Widlar#Fairchild_Semicondu...
- danharaj 7y agoWhat?
- markrages 7y agoThis audience is software developers. They will not have an appreciation for Widlar's genius.
- sumnole 7y agoWhere do all the EEs hang out?
- philiplu 7y agoThanks for the link. I’ve never heard of Wildar before; what an amazing character. Someone had a lot of fun writing that Wikipedia article: “However, the story about Widlar bringing a goat to trim the lawn in front of his office, retold by The New York Times after his death,[14] was incorrect.[19] It was a sheep, not a goat;[68] Widlar brought her in his Mercedes-Benz convertible for just one day, which included a photo op for the local journalists.[19] According to Pease, Widlar abandoned her in the nearest bar;[19] according to Lojek the sheep was ‘mysteriously stolen’.[68]”
- anyfoo 7y agoHah. I went down the same path! I started with some "light" signal processing for an FPGA based project, and now, 2 years or so later, I'm deep into Laplace and z-transforms (and the foundations required for that). You might enjoy those books, available fully online: https://ccrma.stanford.edu/~jos/ https://ccrma.stanford.edu/~jos/
- bogomipz 7y agoThis book looks great! Thanks for tip. Cheers
- mlevental 7y agohow is that true? which component in a modern processor is akin to an fpga or any ip deployed to an fpga?
- anyfoo 7y agoThe CPU itself? For example, implementing a toy CPU is much much closer to how an actual, non-FPGA CPU works than, say, an emulator. But really anything done on an FPGA should teach you some portion of gate-level logic (yeah yeah, there's LUTs and other specialized cells instead of gates, close enough). And staying above physics, that's how computers work.
- satori99 7y agoI think OP is looking at this the other way around -- meaning that it is perfectly possible to create a soft-core CPU on an FPGA, which is a great way to understand what any processor actually does. I know this, because I started learning and tinkering with this sort of thing a year or so ago, with no prior experience with electronics or hardware design, or a formal comp-sci education. I had decades of programming experience already, but I think I have learned more about the fundamentals of computer science while playing with cheap FPGAs, than I have by just writing code.
- alexhutcheson 7y agoAll the digital logic building blocks of a processor, from comparators to ALUs up to branch predictors and pipelines, can be defined and wired together in an HDL. If you have a sufficiently large FPGA, then you can "run" that HDL specification on the FPGA to get a working processor. It's pretty common for computer engineering students to implement a simple RISC processor (often a simplified MIPS) on an FPGA as a class project. In my experience it was a fantastic way to learn the basics of computer architecture.
- bcheung 7y agoI've been going through the book "But How Do It Know" (not a typo) and it's a great introduction on how to build a CPU from scratch starting from basic transistor working up higher and higher levels of abstraction using a bottom up approach. You don't need a lot of math to understand it at all and is a fairly easy read.
- analog31 7y agoI recently got a TinyFPGA-BX, and have been slowly working through the tutorials. The amusing thing is that, for the actual applications I'm working on, a contemporary microcontroller can actually keep up just fine, and is easier for me to comprehend. Still, one of these days, a use will for an FPGA will crop up for which I'll be glad that I learned.
- srjilarious 7y agoI find this to be true for a lot of applications. Some times it seems like fpgas are hammers looking for a nail. Where they can shine is if you need some odd combination of peripherals attached to a microcontroller: think of something like a uc with 4 uarts or multiple separate i2c buses. Anywhere you need a lot of parallel processing that you can guarantee won't be interrupted, like a video processing pipeline is also a good fit.
- anyfoo 7y agoInterfacing with arbitrary hardware, for example random LCD devices with sometimes proprietary on the wire protocols. (Don't have a graphics chip for that screen? Make yourself a graphics chip for that screen!) Or Digital Signal Processing.
- alexhutcheson 7y agoIf you get a high-end microcontroller like a Cortex-M, you can normally just bit-bang the interfaces to devices that you don't have hardware for. DSP is similar - for a hobby project you're normally better off using a high-end device like a Cortex-A and doing the processing in software, rather than futzing with custom digital logic in an FPGA. If you're on a power budget (e.g. for a portable device) you could use a DSP chip like the C6000, but writing the software for it is pretty complicated if you haven't used one before. If you're building a device that's going to be mass-produced and sold, then the situation is different and using FPGAs can make sense, because you'll amortize the engineering cost for the digital logic across all the units you sell. It can be worth it if it lets you use a cheaper processor or microcontroller.
- cowbellemoo 7y ago
- omeze 7y agoThis is a pretty nice tutorial! My courses in FPGA design in school taught me a ton about 1) concurrency and 2) good state machine design. In modern backend web development these topics receive so little attention (from interviewing all the way to writing technical specs, I've rarely encountered these topics brought up explicitly) but are important. I was a bit hesitant for this guide to suggest using C++ since I tend to dislike mixing traditional languages with hardware languages but I realized it was just for testbenches, which is very reasonable (and even VHDL exposes things like `for` loops that are really only useful for testing and meaningless otherwise - sans some special cases[1]). [1] You can abuse some imperative paradigms to implement things like Conway's Game of Life as a systolic array - https://en.wikipedia.org/wiki/Systolic_array https://en.wikipedia.org/wiki/Systolic_array
- srjilarious 7y agoI agree about using C++ for actual ip block implementation. My experience has been pretty mixed. Mostly because the tools (Intel HLS in my case) don't always give you a great idea of what constructs cause you to generate inefficient hdl code. For example, passing a variable by reference in one context cost me an extra 10% logic blocks, and in another lowered it by 10%. It became a bit of a shotgun approach to optimising
- jeffreygoesto 7y agoOne does not pass a variable in an HDL design ;-). Trying to pluck software principles onto FPGAs is wasting so much performance. Get one with the underlying hardware and map your problem onto them, not an intermediate SW-like representation. Like some other comment mentioned, get one with the clock and your design will fly.
- scott_wilson46 7y agoI disagree about for loops, you actually end up using these quite a lot in vhdl/verilog (with understanding about what logic you are going to end up with), if you want to do the same operation on multiple things: input [NUM_OF_MULTIPLIERS*32-1:0] a_in, input [NUM_OF_MULTIPLIERS*32-1:0] b_in, output [NUM_OF_MULTIPLIERS*64-1:0] mult_out reg [31:0] tmp_a, tmp_b; reg [63:0] tmp_mult; always @(*) begin mult_out = {(NUM_OF_MULTIPLIERS*64){1'b0}}; for (i=0; i<NUM_OF_MULTIPLIERS; i+=1) begin tmp_a = a_in>>(i*32); tmp_b = b_in>>(i*32); tmp_mult = tmp_a*tmp_b; mult_out |= tmp_mult<<(i*64); end end Would give you NUM_OF_MULTIPLIERS multipliers. If you wrote each multiply out, it would be more code and also wouldn't allow you to parametrize the code.
- vvanders 7y agoGreat article, I wish the discussions around clocks had gone a bit more into how the tradeoff of pipelining vs longest operation ends up impacting designs. That and SRAM vs DRAM access latencies were the things that really connected the dots from how performance optimization on the software side of things is rooted in physical hardware limitations.
- bogomipz 7y agoMight you or anyone else have some links or references you could share on these two topics? Was there a specific book that helped connect the dots that you could recommend?
- jeffreygoesto 7y agoSorry, no book reference. What is important to realize is that computing can be seen as a 4D problem. Get the right data to the right processing unit at the right clock cycle. This applies to CPU and GPU as well, but got forgotten under a plethora of abstraction layers.
- mng2 7y agoHere's a greatly simplified example. Let's say you're trying to calculate y = mx + b in your FPGA. You want this operation to run at 100 MHz. Great, you write the code, synthesize and implement. Uh oh, the tools report that your design has failed timing analysis. What now? Looking at the output of the tools, they'll say something like "x to y setup time: -2 ns slack". That means your desired operation can't meet the 10 ns clock period; it actually takes 12 ns for all the logic to ripple through. So now what? You can break up the operation into two steps. Let's say the multiplication takes 8 ns, and the addition takes 4 ns. In timestep 1 you do z = mx, and pipeline c = b. Then in timestep 2 you do y = z + c. This way your operation takes two clock cycles = 20 ns total in terms of latency, but you can maintain a rate of 100 MHz. Alternatively, you could choose a slower clock rate, say 75 MHz, and have a clock period of 13.333 ns. Then you would be able to meet the logic delay requirements in one cycle. Again this is greatly simplified but it's similar to what one ends up doing in real FPGA designs. At the beginning you're usually trying to achieve maximum performance. Then later on you add more features to the FPGA, only to find that in doing so, you've caused an existing portion of the design to fail timing, so you need to twiddle things around.
- jeremycw 7y agoI wrote tetris in verilog that can output to VGA 10 years ago for a university project. The code is here: https://github.com/jeremycw/tetris-verilog https://github.com/jeremycw/tetris-verilog for anyone interested. Comments are sparse but it might be interesting for anyone looking for some example code that's relatable.
- kpmcc 7y agoFor people who are curious about FPGAs looking to dip their toes in, I’d highly recommend taking a look at cocotb https://github.com/cocotb/cocotb https://github.com/cocotb/cocotb It’s kind of similar to verilator, in that it lets you write test benches for your designs in programming languages as opposed to HDL. Whereas verilator lets you write c++, cocotb is python based. Both of these are probably best to take up after spending some time with an hdl, so you learn to think from a hardware perspective. Also check out the zipcpu blog
- shaklee3 7y agoSmall error in the article: 200*10e6 is 2GHz, not 200MHz.
- srjilarious 7y agoHa, good eye. corrected to 1e6 :)
- topspin 7y agoNice work. FPGA design appears to be very similar to GPU shader programming. First time I've read anything about FPGA design that connected. Usually FPGA stories get lost in data flow jargon and I learn nothing.
- tverbeure 7y agoI don’t really see how FPGA programming is similar to shader programming.
- lnsru 7y agoThere is no programming in FPGA at all. You describe your hardware using hardware description languages like VHDL or Verilog.
- rowanG077 7y agoThen no programming exists at all. When writing a C code you are describing a program that runs on the C abstract machine. The same thing holds for all "programming" languages.
- lnsru 7y agoSorry, I am not ready for philosophical discussion. We can take definition from Wikipedia: https://en.m.wikipedia.org/wiki/Computer_programming https://en.m.wikipedia.org/wiki/Computer_programming Programming involves code execution on computer. There is no computer in FPGA.
- dopeboy 7y agoTen years ago, in grad school, I co-wrote a video conferencing module in VHDL [0]. I haven't touched HDLs since but here's what I remember very clearly from that project: * It took > 3 minutes to compile our code. * DMA made a huge performance difference once we figured it out. * Realizing that we had to be one with the clock tick took a lot of time. Understanding synchronous based programming (if that's the term) was a paradigm shift for my partner and I. * The utter delight when we got frames streaming across the wire. The performance (though over a LAN) was silky smooth and you could tell immediately this was different than the run-of-the-mill x86 desktop program. [0] - http://www1.cs.columbia.edu/~sedwards/classes/2009/4840/reports/RVD.pdf http://www1.cs.columbia.edu/~sedwards/classes/2009/4840/repo...
- xvilka 7y agoThe problem of FPGAs is their proprietary nature, and Verilog/VHDL are far from the best languages. Gladly there is a number of open-source projects aiming to close this gap - Yosys[1], SymbiFlow[2], Chisel3[3]/FIRRTL[4]. Some time ago I suggested[5] different open source projects should unite and reuse the common intermediate language, akin to LLVM in many software development and analysis tools. From my point of view, FIRRTL is the best designed one, there is a huge problem of being implemented in Scala though, especially for C/C++/etc written projects. Hopefully, there will be more collaboration one day. Either reimplementation from scratch, e.g. in Rust or C++, or using Scala Native. [1] https://github.com/YosysHQ https://github.com/YosysHQ [2] https://symbiflow.github.io/ https://symbiflow.github.io/ [3] https://www.chisel-lang.org/ https://www.chisel-lang.org/ [4] https://www.chisel-lang.org/firrtl/ https://www.chisel-lang.org/firrtl/ [5] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19
- piadodjanho 7y agoJust want add Spatial [1] to your list. It is a inovative high level language, very different from the the traditional HDL. [1] https://spatial-lang.org/ https://spatial-lang.org/
- Ericson2314 7y agoDon't forget https://clash-lang.org/ https://clash-lang.org/ I've used it a bunch and its real life. I both understood what the compiled circuit would be better and could make powerful abstraction. So a better high level and low level language at the same time!
- rowanG077 7y agoThis is true!!! The real problem for me is the IP's. You really do need a DDR SDRAM controller for a lot of real project. Or a PCIE IP to communicate with external resources. If I just use the proprietary tooling it's just a click away to integrated this into a project. Open source has no answer for this as of yet. Now that we have some nice FPGA's we can use I think this is the next biggest hurdle.
- ernst_klim 7y ago
- SemiTom 7y agoFPGAs are getting larger, more complex, and significantly harder to verify and debug https://semiengineering.com/fpga-design-tradeoffs-getting-more-difficult/ https://semiengineering.com/fpga-design-tradeoffs-getting-mo...
- HNLurker2 7y agoWow this is a gift from God. I was doing fpga for my CV and this just made my life a lot easier
- nan0 7y agoCool! Back in college we used fpgas with verilog! The labs always took some finagling to get working, but still very fun!
- lnsru 7y agoI am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications. What I am missing are 2 topics: timing analysis and debugging. Static timing analysis and proper timing constrains are crucial for functional design. No tool can differentiate without constrains a slow signal signal toggling LED every 10 seconds from DDR3 533 MHz differential clock line. Debugging FPGAS design cannot be avoided. Even if design works in simulator, it fails very often on real hardware. And then real fun starts. Xilinx has Integrates Logic Analyzer, Intel has Chipscope. Other vendors have their own similar tools. There are best FPGA designer’s friends. But these tools can’t be trusted, they break sometimes design in unexpected ways. Designer must develop gut feeling, what’s happening. Synthesis of design with integrated logic analyzer takes much more time than regular one. Debugging cycles are insane long. Forgetting one signal can mean 2 hours waiting, so add them all at very beginning. Writing hardware description language is easy part. As somebody already mentioned, everybody can count ones and zeros. First problem every software engineer encounters is simple: there is nothing to program. FPGA design is about describing your system with these ancient language. Second problem is using bulky toolchain. It’s more than compile and debug buttons. In fact, there is huge machine processing code to bitstream. And it’s complexity naturally takes time to understand, you don’t need to be smart to be FPGA designer.
- q3k 7y ago> I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications. Probably because it has very limited support in open source tooling, same as VHDL.
- orbifold 7y agoThat is not true: Verilator is an excellent tool that compiles a large subset of synthesizable System Verilog to C++. Companies like Tesla use it and report speed ups of up to 40 compared to commercial tools. Similarly for vhdl there exists ghdl, which seems pretty feature complete and has an LLVM backend
- 7y ago
- tehsauce 7y agoGood reference!
- omgtehlion 7y agolittle nitpick: it's "combinational circuits", not "combinatorial" (that's whole another part of math)
- kingosticks 7y agoDo you have a reference for that? I'm genuinely curious since both terms are used in literature.
- omgtehlion 7y ago"combinatorial" was used predominantly in 1970s books for whatever reason. In most of contemporary books and university courses "combinational" is used and with a note that you should not confuse it with "combinatorics" and "combinatory logic"
- jonsen 7y ago“An alternate term is combinatorial logic,[2] though this usage may be considered controversial.[3]”: https://en.m.wikipedia.org/wiki/Combinational_logic https://en.m.wikipedia.org/wiki/Combinational_logic
- diarmuidc 7y agoThat's a good intro. What I always have to remind software guys who switch to FPGA design is remember each line you write is eventually going to end up in hardware. That means when you write something you should have some understanding of the underlying hardware inferred. So is this going to give me some combinatorial logic, a register or a RAM? It's very easy to keep the software mindset of if it compiles then it's good.
- denton-scratch 7y agoThank you, that was interesting. I've programmed microcontrollers, but I've never tangled with ASICs or FPGAs. Too scared, I guess. Your article has reduced my fear (and also, you mentioned the price of that Tiny FPGA board; at that price point, I don't mind too much if the magic smoke gets out).
- CommieDetector 7y agoKeep the Python loving freaks away from my FPGAs
- Vysero 7y agoIf any of you are interested in FPGA's after reading the article I highly recommend: Introduction to Logic Circuits & Logic Design with VHDL by Brock J LaMeres He was my instructor in college and the text itself is extremely helpful for all things FPGA.
- matiszek23 7y agoTrue