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Right now DDR3 is made on a ~30nm process. We can't really shrink that too much more without the various pathways bleeding into each other. We're just running
by redthrowaway 16y ago
Right now DDR3 is made on a ~30nm process. We can't really shrink that too much more without the various pathways bleeding into each other. We're just running into insulation limits. They'll still be able to shrink it a bit, but this holds true for CPUs as well, and is one of many reasons why we're increasing cores in pursuit of higher performance.
We're scheduled to hit 11nm; after that I'm not sure. See the Wikipedia article on quantum tunnelling for an explanation that's mostly above my comprehension.
http://en.wikipedia.org/wiki/Quantum_tunnelling http://en.wikipedia.org/wiki/Quantum_tunnelling
edit: To get an idea of the scales we're talking about, 11nm is only about 50 silicon atoms wide.
http://www.wolframalpha.com/input/?i=11nm+/+width+of+silicon+atom http://www.wolframalpha.com/input/?i=11nm+/+width+of+silicon...
- fhars 16y agoA back of the envelope calculation says that a linear shrink with a factor of three means nine times as many structures on a given die area. This is consistent with the factor of ten in a decade. There will be hard technical problems lurking in the details, but the end is not yet nigh.
- bdonlan 16y agoThat just means we need to move to a three-dimensional process. Speaking of which, aren't memristors supposed to be layerable?