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> requires some care when selecting your gear Doesn't that mostly boil down to "avoid anything newer than Ivy Bridge/Bulldozer"? > high performance memory […]

> requires some care when selecting your gear Doesn't that mostly boil down to "avoid anything newer than Ivy Bridge/Bulldozer"? > high performance memory […] controller function blocks There are DDR4 controllers with FOSS training code out there :) https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/tree/mv_ddr-armada-atf-mainline https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/...

tpearson-raptor 7y ago
Here's POWER's training code for DDR4: https://git.raptorcs.com/git/talos-hostboot/tree/src/import/chips/p9/procedures/hwp/memory https://git.raptorcs.com/git/talos-hostboot/tree/src/import/... pgeorgi has a valid point in that if you go for the cheapest off the shelf building block type DDR4 solution for your silicon design (won't name names here, but it's a widely known vendor in the silicon block space), those controllers come with mandated binary-only firmware. IBM (and apparently Marvell?) both didn't use that cheap off the shelf solution and also decided to release their training code. Kudos to both companies for bucking the trend here!
- pgeorgi 7y ago
  That cheapest COTS block also has the advantage of being battle tested by the big customer base. Since you presumably have pretty good contacts into IBM: ever asked if they'd consider pooling resources with other vendors around their interconnects in an open forum? Not sure if DDR4 (or USB, or even PCIe 4.0) silicon is a huge differentiator for them, and those protocols all thrive on interoperability: no need for IBM (or Marvell, for example) to figure out all the issues with real world peripherals on their own.
  - tpearson-raptor 7y ago
    The general answer is yes and yes. That's why OMI / OpenCAPI are being released as standards, with RTL / HDL. I think at this point there would be more appetite for a next gen interface like DDR5 vs. DDR4 to be released, but I'm just speaking personally from general knowledge here.

tpearson-raptor 7y ago

Here's POWER's training code for DDR4: https://git.raptorcs.com/git/talos-hostboot/tree/src/import/chips/p9/procedures/hwp/memory https://git.raptorcs.com/git/talos-hostboot/tree/src/import/... pgeorgi has a valid point in that if you go for the cheapest off the shelf building block type DDR4 solution for your silicon design (won't name names here, but it's a widely known vendor in the silicon block space), those controllers come with mandated binary-only firmware. IBM (and apparently Marvell?) both didn't use that cheap off the shelf solution and also decided to release their training code. Kudos to both companies for bucking the trend here!

pgeorgi 7y ago
That cheapest COTS block also has the advantage of being battle tested by the big customer base. Since you presumably have pretty good contacts into IBM: ever asked if they'd consider pooling resources with other vendors around their interconnects in an open forum? Not sure if DDR4 (or USB, or even PCIe 4.0) silicon is a huge differentiator for them, and those protocols all thrive on interoperability: no need for IBM (or Marvell, for example) to figure out all the issues with real world peripherals on their own.
- tpearson-raptor 7y ago
  The general answer is yes and yes. That's why OMI / OpenCAPI are being released as standards, with RTL / HDL. I think at this point there would be more appetite for a next gen interface like DDR5 vs. DDR4 to be released, but I'm just speaking personally from general knowledge here.