4 ms·
Why is no branch delay slots a bad thing?
by colejohnson66 7y ago
Why is no branch delay slots a bad thing?
- magicalhippo 7y agoYou read that wrong. GP said branch delay slots are a dumb thing, and the RISC V doesn't have it. More details on Wikipedia[1], and there's some nice answers as to why it's a bad idea these days on SO[2]. To summarize, the branch delay slot optimization makes exception handling and debugging much more complicated, doesn't bring much added performance if you have a deep pipeline, and modern branch prediction can render the the branch delay slot optimization moot anyway. It should be said that it wasn't necessarily a dumb thing back in the days, but rather that it's a dumb thing on a modern architecture. [1]: https://en.wikipedia.org/wiki/Delay_slot#Branch_delay_slots https://en.wikipedia.org/wiki/Delay_slot#Branch_delay_slots [2]: https://stackoverflow.com/questions/54724410/why-is-the-branch-delay-slot-deprecated-or-obsolete https://stackoverflow.com/questions/54724410/why-is-the-bran...
- CalChris 7y agoProbably should have been: Why are branch delay slots a bad thing? Branch delay slots were used in early pipelined RISC processors: MIPS, PA-RISC, SPARC. These were short pipelines but not superscalar and not out of order superscalar. Navigating pipeline hazards gets much more complicated with much deeper pipelines, more functional units and out of order execution. Basically, branch delay slots don't scale.