5 ms·
Timing (trade wars, ending days of Moore's law, intels incompetence as of late), marketing (ucb/Stanford), few outright dumb decisions (e.g. no branch delay slo
by deepnotderp 7y ago
Timing (trade wars, ending days of Moore's law, intels incompetence as of late), marketing (ucb/Stanford), few outright dumb decisions (e.g. no branch delay slots), money (DARPA), industrial support (nvidia, western digital, esperanto etc.)
- colejohnson66 7y agoWhy is no branch delay slots a bad thing?
- magicalhippo 7y agoYou read that wrong. GP said branch delay slots are a dumb thing, and the RISC V doesn't have it. More details on Wikipedia[1], and there's some nice answers as to why it's a bad idea these days on SO[2]. To summarize, the branch delay slot optimization makes exception handling and debugging much more complicated, doesn't bring much added performance if you have a deep pipeline, and modern branch prediction can render the the branch delay slot optimization moot anyway. It should be said that it wasn't necessarily a dumb thing back in the days, but rather that it's a dumb thing on a modern architecture. [1]: https://en.wikipedia.org/wiki/Delay_slot#Branch_delay_slots https://en.wikipedia.org/wiki/Delay_slot#Branch_delay_slots [2]: https://stackoverflow.com/questions/54724410/why-is-the-branch-delay-slot-deprecated-or-obsolete https://stackoverflow.com/questions/54724410/why-is-the-bran...
- CalChris 7y agoProbably should have been: Why are branch delay slots a bad thing? Branch delay slots were used in early pipelined RISC processors: MIPS, PA-RISC, SPARC. These were short pipelines but not superscalar and not out of order superscalar. Navigating pipeline hazards gets much more complicated with much deeper pipelines, more functional units and out of order execution. Basically, branch delay slots don't scale.
- 0x64 7y agoMoore’s law is pretty well on track – transistor density has been steadily increasing for decades now, and still is.
- Symmetry 7y agoThings are still shrinking but the tempo seems to be slowing down a bit even at TSMC. Maybe we'll get our full 6 remaining doublings down to 9Å[1] but I'm not sure I would count on it, especially given that the cost of a cutting edge fab is also going up exponentially. Even if features stop shrinking that doesn't mean that price per transistor will stop going down. And we're very far from the theoretical limits of energy per computation so I tend to expect we'll move to some other computational substrate in the future. [1]https://en.wikichip.org/wiki/technology_node https://en.wikichip.org/wiki/technology_node [2]http://www.futrfab.com/wp-content/uploads/2012/04/Small-Volume-Technology-Fabrication_new.pdf http://www.futrfab.com/wp-content/uploads/2012/04/Small-Volu...
- sporkland 7y agoThere are a fair number of folks including Gordon Moore who have said Moore's law will end in the next couple halvings.
- deepnotderp 7y ago1) Slowing is happening and at some point you run out of atoms 2) Usually people mean all of CMOS scaling (ie Dennard Scaling) when they refer to "Moore's law ". Exponential increase in power density is low key useless...