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I've been hoping for some time that someone could make an in-hardware (or FPGA) compressing memory controller or MMU, with low enough latency to be comparable t
by guiriduro 7y ago
I've been hoping for some time that someone could make an in-hardware (or FPGA) compressing memory controller or MMU, with low enough latency to be comparable to memory access, possibly even higher bandwidth (being compressed), and transparent. Would increase the effective memory of SoCs, but also in general. Thinking like zram but realtime. Another one for academia I guess.
- speedplane 7y agoBasically a hardware lookup table, right? Potentially fast to read, but impossibly slow to write as you’d need to reprogram an FPGA. Still a cool concept.
- guiriduro 7y agoI had in mind something like several parallel hardware LZ codecs sitting at the border between the CPU caches and memory, along with some VM driver software. Given CPU writes would go to caches first (as managed by cache-coherency logic), they would remain fast to read, only at the point a flush is triggered would a codec have to write a compressed page to memory - which may be slower than uncompressed. I'd imagine there would need to be a bunch of experimental work to determine page size and other parameters, which may even be application-specific tunables.
- fulafel 7y agoThere is one specialized area this is widely done in: hw texture compression in GPUs. Buts it's read only and not automatic.
- atq2119 7y agoGPUs also do lossless transparent compression in some places for bandwidth reduction, at the cost of allocating some additional metadata. It's commonly called delta color compression. (And it doesn't reduce memory allocations, but it fits the theme here.)