Preference for NAND and negative logic (ie. active low) do not stem from early CMOS, but from TTL. TTL NAND is same structure as invertor, only with multiple em

Preference for NAND and negative logic (ie. active low) do not stem from early CMOS, but from TTL. TTL NAND is same structure as invertor, only with multiple emitters on the input transistor. And with TTL significant current flows only in the low state, typical TTL gate sees undriven input as logic 1. By the way for CMOS, NOR is somewhat counter-intuitively still preferable as the two series connected PMOS pull-up transistors can be collapsed into one dual-gate PMOS, which leads to more desirable gate geometry. This is the reason why CMOS CD4000 is NOR (and without looking it up I don't even know what is the P/N of 4000-series 2-input NAND), while TTL SN7400 is NAND. On the other hand in modern CMOS processes and particularly in CMOS VLSI design this distinction is mostly moot.