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NAND or NOR preference is due to the underlying transistor technology. NPN transistors (with electron majority carriers) tend to be stronger than PNP types (wit
by fspeech 7y ago
NAND or NOR preference is due to the underlying transistor technology. NPN transistors (with electron majority carriers) tend to be stronger than PNP types (with hole majority carriers) at comparable sizes. In the beginning we had mostly bipolar processes, where we used NPN transistors in parallel to pull down the output and pull-ups were simply resistors. NOR gate was the natural configuration efficiency/cost wise. Later CMOS processes came along and we no longer use resistors for pull-ups (which tremendously reduces the quiescent current and makes CMOS perfect for digital logic). With CMOS it makes more sense to use the weaker PMOS (PNP) transistors in parallel for pull up and use the stronger NMOS (NPN) transistors in series for pull down and the natural configuration is the NAND gate.
- dfox 7y agoPreference for NAND and negative logic (ie. active low) do not stem from early CMOS, but from TTL. TTL NAND is same structure as invertor, only with multiple emitters on the input transistor. And with TTL significant current flows only in the low state, typical TTL gate sees undriven input as logic 1. By the way for CMOS, NOR is somewhat counter-intuitively still preferable as the two series connected PMOS pull-up transistors can be collapsed into one dual-gate PMOS, which leads to more desirable gate geometry. This is the reason why CMOS CD4000 is NOR (and without looking it up I don't even know what is the P/N of 4000-series 2-input NAND), while TTL SN7400 is NAND. On the other hand in modern CMOS processes and particularly in CMOS VLSI design this distinction is mostly moot.