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Back in the 1990s, UC Berkeley's computer hardware quals exam used to require the test taker to design a microcoded RISC processor out of NAND gates, from the b

by not2b 7y ago

Back in the 1990s, UC Berkeley's computer hardware quals exam used to require the test taker to design a microcoded RISC processor out of NAND gates, from the bottom up. It was kind of like Little Alchemy, once you created every kind of primitive gate you needed, you could assemble them to make larger and larger things. This included building latches, registers, static RAM, bottom to top. NOR is just NAND with 0's and 1's reversed.

djhworld 7y ago
This is pretty much the approach I took a few months back after reading _But how do it Know?_ by J. Clark Scott, although I wrote it in software [1] [1] https://medium.com/swlh/i-dont-know-how-cpus-work-so-i-simulated-one-in-code-bd85f216b49 https://medium.com/swlh/i-dont-know-how-cpus-work-so-i-simul...
fahrradflucht 7y ago
That is basically the premise of the awesome Nand2Tetris[0] book/project. [0] https://www.nand2tetris.org/ https://www.nand2tetris.org/ Edit: Just saw that it is even referenced[1] in the article itself. [1] https://www.righto.com/2019/09/a-computer-built-from-nor-gates-inside.html#fn:nand https://www.righto.com/2019/09/a-computer-built-from-nor-gat...
saagarjha 7y ago
One of the classes at my university had a tradition of a guest lecturer coming in and give a two hour talk on “building a computer with magnets” at the beginning of the quarter to incoming freshmen. He’d go through pretty much the same things you mentioned, combining smaller components as he went into more complex ones, culminating in a computer that could do a full fetch-decode-execute cycle (whimsically, powered by the turning of a water wheel).
ip26 7y ago
How much time did you have for this exam? Building a complete processor starting from gates is not exactly a thirty minute exercise, even with a minimal instruction set & narrow datapath.
- frostburg 7y ago
  I recall having to do something similar for my "computer architecture" exam (in Italy) in very limited time (it was on paper during an oral examination), but I could get away with a very simple not-even-pipelining design.
fspeech 7y ago
NAND or NOR preference is due to the underlying transistor technology. NPN transistors (with electron majority carriers) tend to be stronger than PNP types (with hole majority carriers) at comparable sizes. In the beginning we had mostly bipolar processes, where we used NPN transistors in parallel to pull down the output and pull-ups were simply resistors. NOR gate was the natural configuration efficiency/cost wise. Later CMOS processes came along and we no longer use resistors for pull-ups (which tremendously reduces the quiescent current and makes CMOS perfect for digital logic). With CMOS it makes more sense to use the weaker PMOS (PNP) transistors in parallel for pull up and use the stronger NMOS (NPN) transistors in series for pull down and the natural configuration is the NAND gate.
- dfox 7y ago
  Preference for NAND and negative logic (ie. active low) do not stem from early CMOS, but from TTL. TTL NAND is same structure as invertor, only with multiple emitters on the input transistor. And with TTL significant current flows only in the low state, typical TTL gate sees undriven input as logic 1. By the way for CMOS, NOR is somewhat counter-intuitively still preferable as the two series connected PMOS pull-up transistors can be collapsed into one dual-gate PMOS, which leads to more desirable gate geometry. This is the reason why CMOS CD4000 is NOR (and without looking it up I don't even know what is the P/N of 4000-series 2-input NAND), while TTL SN7400 is NAND. On the other hand in modern CMOS processes and particularly in CMOS VLSI design this distinction is mostly moot.

by not2b 7y ago

djhworld 7y ago

This is pretty much the approach I took a few months back after reading _But how do it Know?_ by J. Clark Scott, although I wrote it in software [1] [1] https://medium.com/swlh/i-dont-know-how-cpus-work-so-i-simulated-one-in-code-bd85f216b49 https://medium.com/swlh/i-dont-know-how-cpus-work-so-i-simul...

fahrradflucht 7y ago

That is basically the premise of the awesome Nand2Tetris[0] book/project. [0] https://www.nand2tetris.org/ https://www.nand2tetris.org/ Edit: Just saw that it is even referenced[1] in the article itself. [1] https://www.righto.com/2019/09/a-computer-built-from-nor-gates-inside.html#fn:nand https://www.righto.com/2019/09/a-computer-built-from-nor-gat...

saagarjha 7y ago

One of the classes at my university had a tradition of a guest lecturer coming in and give a two hour talk on “building a computer with magnets” at the beginning of the quarter to incoming freshmen. He’d go through pretty much the same things you mentioned, combining smaller components as he went into more complex ones, culminating in a computer that could do a full fetch-decode-execute cycle (whimsically, powered by the turning of a water wheel).

ip26 7y ago

How much time did you have for this exam? Building a complete processor starting from gates is not exactly a thirty minute exercise, even with a minimal instruction set & narrow datapath.

frostburg 7y ago
I recall having to do something similar for my "computer architecture" exam (in Italy) in very limited time (it was on paper during an oral examination), but I could get away with a very simple not-even-pipelining design.

fspeech 7y ago

NAND or NOR preference is due to the underlying transistor technology. NPN transistors (with electron majority carriers) tend to be stronger than PNP types (with hole majority carriers) at comparable sizes. In the beginning we had mostly bipolar processes, where we used NPN transistors in parallel to pull down the output and pull-ups were simply resistors. NOR gate was the natural configuration efficiency/cost wise. Later CMOS processes came along and we no longer use resistors for pull-ups (which tremendously reduces the quiescent current and makes CMOS perfect for digital logic). With CMOS it makes more sense to use the weaker PMOS (PNP) transistors in parallel for pull up and use the stronger NMOS (NPN) transistors in series for pull down and the natural configuration is the NAND gate.

dfox 7y ago
Preference for NAND and negative logic (ie. active low) do not stem from early CMOS, but from TTL. TTL NAND is same structure as invertor, only with multiple emitters on the input transistor. And with TTL significant current flows only in the low state, typical TTL gate sees undriven input as logic 1. By the way for CMOS, NOR is somewhat counter-intuitively still preferable as the two series connected PMOS pull-up transistors can be collapsed into one dual-gate PMOS, which leads to more desirable gate geometry. This is the reason why CMOS CD4000 is NOR (and without looking it up I don't even know what is the P/N of 4000-series 2-input NAND), while TTL SN7400 is NAND. On the other hand in modern CMOS processes and particularly in CMOS VLSI design this distinction is mostly moot.