3 ms·

What's the technical reason Verilator can be faster?

brandmeyer 7y ago
Strictly speaking, Verilog's machine model is one that passes messages around between its processes. A given `always_ff` process with several statements issues those statements one at a time in the abstract machine. There are a few different simulator technologies out there. A gate-level simulator renders the design into a bunch of SPICE nets and discrete transistors. SPICE then turns the whole shebang into a gigantic sparse matrix solver. This is the highest-fidelity model, and also the slowest. A vendor who owns their own process node might do this. TSMC won't let you see their transistor models or standard cell library. Maybe AMD gets that much visibility. NGSPICE is a FOSS example of this type of simulator, although I don't know of a netlister that ultimately starts from an HDL for it. A message-passing simulator provides a somewhat strict view of the Verilog abstract machine. It executes the elements of each process more or less sequentially, where each assignment issues a new message to the processes that are sensitive to changes on the assigned variable. Its also dog slow. It might seem reasonably accurate, but the quasi-sequential execution model can hide real bugs in hardware that is actually executing in parallel. Icarus Verilog is a FOSS example of this type of simulator. Verilator gets faster a couple of ways. First off, it only implements the synthesizable subset of Verilog. Second, it assumes that all of the flip-flops that are triggered by a clock edge are actually triggered immediately, and cause downstream effects on combinatorial logic immediately. This isn't exactly true, either, since both wire and transistor delay is really a thing. But it is somewhat more true than the message-passing model. In reality all of those transistors are acting simultaneously after all. For the most part, if you stick to synthesizable constructs, write your code in a reasonably high-level fashion, and pay attention to the implementation tool's timing reports, it ends up being true enough. Or, in Verilator's own words: > How can Verilator be faster than (name-the-commercial-big-3-simulator)? > Generally, the implied part of the question is ``... with all of their manpower they can put into it.'' > Most commercial simulators have to be Verilog compliant, meaning event driven. This prevents them from being able to reorder blocks and make netlist-style optimizations, which are where most of the gains come from. > Non-compliance shouldn't be scary. Your synthesis program isn't compliant, so your simulator shouldn't have to be -- and Verilator is closer to the synthesis interpretation, so this is a good thing for getting working silicon.
- person_of_color 7y ago
  Good answer. Do you use Verilator in your org?
  - brandmeyer 7y ago
    Yes. Although, the fact that you have to write your model's driver in C++ is a turn-off for the career HDL engineers. I'm using it to model some DSP accelerators of algorithms that were originally developed in C. So I find the ability to easily run comparison tests side-by-side against the C model to be the best part. The Verilator linter is also pretty good. HDL that can pass the Verilator linter almost has a VHDL-like accent to it.
    - person_of_color 7y ago
      Is your company hiring?
- kingosticks 7y ago
  I've used Modelsim my entire working life and one part of that has been the GUI debugger with it's waveforms, breakpoints, watches, execution stepping etc. If Verilator is re-ordering and optimising blocks, is that all stil possible, or only for the particular subset it doesn't happen to optimise away?
  - brandmeyer 7y ago
    Yes, it is possible. By default, only the top-level nets are exported from any given module. However, you can annotate additional nets of interest for export. There's also a mode whereby you can export everything, at a big hit in speed. Even when exporting everything, its still much faster than Vivado's simulator, though.
    - kingosticks 7y ago
      That's interesting, thanks. The new 'vopt' mode in Modelsim forces you to do the same annotation thing, perhaps they are moving towards a Verilator style approach. Sadly vopt mode doesn't work for some of our designs and actually makes others slower so we have avoided adopting it (and are now stranded on an old version of the tool).

Strictly speaking, Verilog's machine model is one that passes messages around between its processes. A given `always_ff` process with several statements issues those statements one at a time in the abstract machine. There are a few different simulator technologies out there. A gate-level simulator renders the design into a bunch of SPICE nets and discrete transistors. SPICE then turns the whole shebang into a gigantic sparse matrix solver. This is the highest-fidelity model, and also the slowest. A vendor who owns their own process node might do this. TSMC won't let you see their transistor models or standard cell library. Maybe AMD gets that much visibility. NGSPICE is a FOSS example of this type of simulator, although I don't know of a netlister that ultimately starts from an HDL for it. A message-passing simulator provides a somewhat strict view of the Verilog abstract machine. It executes the elements of each process more or less sequentially, where each assignment issues a new message to the processes that are sensitive to changes on the assigned variable. Its also dog slow. It might seem reasonably accurate, but the quasi-sequential execution model can hide real bugs in hardware that is actually executing in parallel. Icarus Verilog is a FOSS example of this type of simulator. Verilator gets faster a couple of ways. First off, it only implements the synthesizable subset of Verilog. Second, it assumes that all of the flip-flops that are triggered by a clock edge are actually triggered immediately, and cause downstream effects on combinatorial logic immediately. This isn't exactly true, either, since both wire and transistor delay is really a thing. But it is somewhat more true than the message-passing model. In reality all of those transistors are acting simultaneously after all. For the most part, if you stick to synthesizable constructs, write your code in a reasonably high-level fashion, and pay attention to the implementation tool's timing reports, it ends up being true enough. Or, in Verilator's own words: > How can Verilator be faster than (name-the-commercial-big-3-simulator)? > Generally, the implied part of the question is ``... with all of their manpower they can put into it.'' > Most commercial simulators have to be Verilog compliant, meaning event driven. This prevents them from being able to reorder blocks and make netlist-style optimizations, which are where most of the gains come from. > Non-compliance shouldn't be scary. Your synthesis program isn't compliant, so your simulator shouldn't have to be -- and Verilator is closer to the synthesis interpretation, so this is a good thing for getting working silicon.

person_of_color 7y ago
Good answer. Do you use Verilator in your org?
- brandmeyer 7y ago
  Yes. Although, the fact that you have to write your model's driver in C++ is a turn-off for the career HDL engineers. I'm using it to model some DSP accelerators of algorithms that were originally developed in C. So I find the ability to easily run comparison tests side-by-side against the C model to be the best part. The Verilator linter is also pretty good. HDL that can pass the Verilator linter almost has a VHDL-like accent to it.
  - person_of_color 7y ago
    Is your company hiring?
kingosticks 7y ago
I've used Modelsim my entire working life and one part of that has been the GUI debugger with it's waveforms, breakpoints, watches, execution stepping etc. If Verilator is re-ordering and optimising blocks, is that all stil possible, or only for the particular subset it doesn't happen to optimise away?
- brandmeyer 7y ago
  Yes, it is possible. By default, only the top-level nets are exported from any given module. However, you can annotate additional nets of interest for export. There's also a mode whereby you can export everything, at a big hit in speed. Even when exporting everything, its still much faster than Vivado's simulator, though.
  - kingosticks 7y ago
    That's interesting, thanks. The new 'vopt' mode in Modelsim forces you to do the same annotation thing, perhaps they are moving towards a Verilator style approach. Sadly vopt mode doesn't work for some of our designs and actually makes others slower so we have avoided adopting it (and are now stranded on an old version of the tool).