4 ms·
"Power turned out to be a major constraint. At a chip’s standard 1-volt supply, the wafer’s narrow wiring would consume a full 2 kilowatts. Instead, we chose to
by jpm_sd 7y ago
"Power turned out to be a major constraint. At a chip’s standard 1-volt supply, the wafer’s narrow wiring would consume a full 2 kilowatts. Instead, we chose to up the supply voltage to 12 V, reducing the amount of current needed and therefore the power consumed. That solution required spreading voltage regulators and signal-conditioning capacitors all around the wafer, taking up space that might have gone to more GPU modules."
Uh, this seems like a pretty serious downside.
- deleted 7y ago[deleted]
- jjoonathan 7y agoAlso: shifting PCB prototype costs in the direction of silicon is going to be a tough sell for many applications. > Another drawback of SoCs is their high one-time design and manufacturing costs, such as the US $2 million or more for the photolithography masks > ... 6 paragraphs later ... > Patterning wafer-scale Si-IF may require innovations in “maskless” lithography.
- willis936 7y agoResistive losses are that high? The signal integrity issues are going to cause unacceptably high error rates.
- baybal2 7y agoSilicon's limit is 0.7V and there is no trick against that. No matter how efficient is your power supply, you will be losing electricity very very rapidly within single centimetres. That's why there is no way to work around the need to move the voltage conversion on chip. In the future we may even increase IC voltage to reduce the copper losses for very low power, but huge devices.