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Question for experts in the field: are there any reasonable FPGA options capable of hosting a small (~2MiB) quantized deep learning model for which there's any
by m0zg 7y ago
Question for experts in the field: are there any reasonable FPGA options capable of hosting a small (~2MiB) quantized deep learning model for which there's any sort of a viable, open toolchain?
I've looked into some of Lattice's stuff, and some of their chips seem pretty capable for this, but as with all the other FPGA manufacturers, the toolchain is crazy proprietary. I'm not a huge fan of sinking my time into tooling I have no control over.
- analognoise 7y agoThere is an open source syntheses and bitstream generation for some lattice devices. It has inferior QoR compared to the closed toolchain.
- robert_foss 7y agoI think in one of the CCCamp19 talks, the ECP5 routing with the OpenSource tooling blew the Lattice tooling out of the water. FPGA manufacturers have pretty perverse incentives when it comes to filling your FPGA devices up with useless junk.
- analognoise 7y agoLink to talk? My Google Fu fails me.
- buildbot 7y agoYes! Most Cyclone Vs or Zync/Artix chips can support quantized networks, and people have been making them easier to get started with, for example this toolchain[1]: https://github.com/danielholanda/LeFlow https://github.com/danielholanda/LeFlow Can take Tensorflow models and convert them to Verilog. Tensorflow already has lots of tools to train quantized models, so all you need to do is convert them to hardware. If you had a big enough Lattice FPGA you the open source Yosys toolchain, or use one of the Vendor proprietary toolchains for Altera/Xilinx. [1] Disclaimer - I went to school with the creator of LeFlow.
- robert_foss 7y agoThe Lattice ECP5 is supported by open source tooling, does it support your usecase otherwise?