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It is expensive to tape out a different chip. As 8051 originally was about 50000 transistors that’s peanuts nowadays. Likely cheaper to manufacture a single ch

It is expensive to tape out a different chip. As 8051 originally was about 50000 transistors that’s peanuts nowadays. Likely cheaper to manufacture a single chip and do market segmentation via software than manufacture two if the savings are measly (let’s assume 16nm process) 1/500 mm^2 per chip.

bhouston 7y ago
Intel only taps out about three different dies per generation line I believe. For example the Skylake-SP line just has LCC, HCC and XCC dies, and the the whole multitude of their product line comes from those three. https://investorshub.advfn.com/boards/read_msg.aspx?message_id=141418711 https://investorshub.advfn.com/boards/read_msg.aspx?message_...
close04 7y ago
I think these are actually built on 150nm process. Using a modern process like 16nm would command some hefty premiums, and some redesign work. This is what old fabs end up manufacturing: high volume, low cost ICs. But you're right about the rest. The segmentation is achieved with fuses and firmware.
mbell 7y ago
It's not so much the 'core' as the memory. For example it looks like the RTL8367 has 16KB of program memory, 32KB of data memory, 256bytes of SRAM and a 12KB nic buffer. These memory cells will make up the bulk of the transistors in the 8051 part of the chip and tend to be points of manufacturing failure. In many cases the chip would be designed with more memory than it needs under the assumption there will always be a few failures. So if you need 16KB, you design in 18KB and turn off the rows/banks that fail or test as the worst. If too many fail you sell it as next memory size down, or in this case you zap a couple fuses and sell it as the part without an MCU on board. Of course this doesn't always work, sometimes you need more of the non-perfect parts than you have to fill orders so you just zap the fuses anyway.
0xcde4c3db 7y ago
There are also chips that support two different feature sets via a mode pin, but instead of documenting the mode pin, the modes are sold as separate products with the mode pin simply labeled as Vcc/ground/NC.

bhouston 7y ago

Intel only taps out about three different dies per generation line I believe. For example the Skylake-SP line just has LCC, HCC and XCC dies, and the the whole multitude of their product line comes from those three. https://investorshub.advfn.com/boards/read_msg.aspx?message_id=141418711 https://investorshub.advfn.com/boards/read_msg.aspx?message_...

close04 7y ago

I think these are actually built on 150nm process. Using a modern process like 16nm would command some hefty premiums, and some redesign work. This is what old fabs end up manufacturing: high volume, low cost ICs. But you're right about the rest. The segmentation is achieved with fuses and firmware.

mbell 7y ago

It's not so much the 'core' as the memory. For example it looks like the RTL8367 has 16KB of program memory, 32KB of data memory, 256bytes of SRAM and a 12KB nic buffer. These memory cells will make up the bulk of the transistors in the 8051 part of the chip and tend to be points of manufacturing failure. In many cases the chip would be designed with more memory than it needs under the assumption there will always be a few failures. So if you need 16KB, you design in 18KB and turn off the rows/banks that fail or test as the worst. If too many fail you sell it as next memory size down, or in this case you zap a couple fuses and sell it as the part without an MCU on board. Of course this doesn't always work, sometimes you need more of the non-perfect parts than you have to fill orders so you just zap the fuses anyway.

0xcde4c3db 7y ago

There are also chips that support two different feature sets via a mode pin, but instead of documenting the mode pin, the modes are sold as separate products with the mode pin simply labeled as Vcc/ground/NC.