5 ms·
I guess 3nm is just marketing, but I’d be interested in better understanding the feature sizes here and in current processes. From what I can tell, in their cu
by new299 7y ago
I guess 3nm is just marketing, but I’d be interested in better understanding the feature sizes here and in current processes.
From what I can tell, in their current 5nm process the smallest features are on the order of 30nm? Is that correct? [1] I guess what I’d really like to see is some structures and annotation showing feature sizes. These rarely seem to be shown.
[1] https://en.wikipedia.org/wiki/5_nanometer https://en.wikipedia.org/wiki/5_nanometer
- fspeech 7y agoTransistor (FINFET) width should be around 7nm for the 7nm process (https://en.wikichip.org/wiki/7_nm_lithography_process https://en.wikichip.org/wiki/7_nm_lithography_process) but you are right that transistor pitch isn't scaling nearly as fast so transistor density is not going up as fast. Cost per transistor was actually flat (maybe even going up) at the 7nm node.
- atq2119 7y agoWhat's perhaps even worse is that metal pitch doesn't scale as fast. As a consequence, the ratio of wiring space per transistor has been decreasing for a couple of nodes now, which makes wiring much more difficult and makes it more difficult to use all the transistor area effectively. Basically, designs more frequently have to reduce their density of useful transistors in order to be able to lay down the wiring connections. The number of metal layers can be increased to fight back against this effect somewhat, but you still need space for vias to go through the lowest metal layers, and with design rules getting more complex placing those vias is itself getting tougher (though obviously EUV for metal layers helps there because it allows the design rules to become a bit more relaxed).
- deleted 7y ago[deleted]