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The biggest upgrade over Threadripper 1950X is that the new ones are no longer NUMA. So performance across the cores will be much more consistent even if the pe
by kllrnohj 7y ago
The biggest upgrade over Threadripper 1950X is that the new ones are no longer NUMA. So performance across the cores will be much more consistent even if the peaks are not that much bigger.
If your development involves compiling code then the 2x larger L3 is also going to result in huge improvements to code compilation speed as seen in the Epyc Rome reviews. Example: https://www.phoronix.com/scan.php?page=article&item=amd-epyc-7502-7742&num=5 https://www.phoronix.com/scan.php?page=article&item=amd-epyc... - compare the 7601 vs. the 7502. Both are 32c/64t parts. Both have close-enough base clocks & turbo clocks. But the new one (7502) absolutely smokes the old one (7601) at both kernel compile in GCC and LLVM compile. Compilers love that L3 it seems.
All signs point to Threadripper 3000 still being sTR4 compatible, so that means you could drop in a CPU that gives you +15% single core performance vs. previous gen's best case, no more NUMA domains bringing more consistent performance, lower power usage, and double the L3 for much faster compiles.
That's pretty awesome particularly given we're only talking a ~2 year gap between the products.
- loeg 7y agoWait in what sense are the new Threadrippers no longer NUMA? Edit: Found the Zen 2 Epyc marketing materials that describe this. Yes, apparently memory access on a single socket is uniform, in that all memory access is indirected over the IO chiplet[1]! This may hurt best-case access latency for NUMA-aware workloads? Just speculating. It's not like non-local caches go away with uniform DRAM access latencies — unless L1/L2/L3 are also non-local to the core and indirected behind the IO chiplet. Which would be really surprising. [1]: https://www.servethehome.com/amd-epyc-7002-series-rome-delivers-a-knockout/4/ https://www.servethehome.com/amd-epyc-7002-series-rome-deliv...
- kllrnohj 7y agoIn the definition sense? It's a single memory controller on the IO die & one memory domain. The chiplets don't have their own memory controllers. By contrast Threadipper 1 & 2 had multiple memory controllers. It was 2x dual-channel controllers. As such they were full on real NUMA, just like a multi-processor system.
- loeg 7y agoI was just looking for a source for the claim. Found my own pretty low-detail source; if you've got something better, I'd love to learn more.
- paulmd 7y agoThreadripper 1000/2000 (and corresponding Epyc) were true NUMA: each chiplet had IO for PCIe and memory onboard, and each die handled part of it. Thus you have "near" and "far" memory like a traditional NUMA. On Zen2 everything goes through the IO die. In a sense this means everything is "far" now, but it is uniform, and performance seems to be very good despite this (perhaps due to the insane amount of cache meaning less need to hit memory as frequently).