2 ms·
Trivia: MIPS and RISC-V have the r0 register equal to zero to optimize this case in a more elegant way.
by epx 7y ago
Trivia: MIPS and RISC-V have the r0 register equal to zero to optimize this case in a more elegant way.
- will4274 7y agoSo does x64, almost. More accurately, so do the underlying Intel and AMD micro-archs that host x64.