Well...no. what it says is there are limits on how small of wires we can make, and how small of layers make a material functional (about 5). Wires can't get sm

Well...no. what it says is there are limits on how small of wires we can make, and how small of layers make a material functional (about 5). Wires can't get smaller without compromising RC (and thus speed). Quite horrifically: this is way more an issue than the transistor. Graphene and photonics don't help this. At all. It isn't a matter of how small a tube. You physically need 5nm to insulate, and 5nm for a functional material. So a 5nm device with a 5nm spacer and a 5nm space to the next device is about it. The smallest pitch of any physical device is 20nm. The critical pitches in wafer are about 30nm and 40nm, so in an ideal world, we can reach 3x, ever. It doesn't matter which material you choose. And yeah, you can stack up, but not in quite the way you dream, and thermal and processing issues make this hard in most domains. When I build, I deposit at temperatures, which affect underlying layers. So stacking doesn't quite work as you might expect. Again, real materials Ina real flow are actually different, and not in a trivial 'just make it work' reducible fashion. Memristors may not really exist, and are useful in the context of high speed memory. That has real physical challenges. And people.have spent billions for decades on this problem. Anyway, this is missing some background, but the presentation is great.