This ties in nicely with chiplets: https://semiengineering.com/the-chiplet-race-begins/ https://semiengineering.com/the-chiplet-race-begins/ - a way to integrat

This ties in nicely with chiplets: https://semiengineering.com/the-chiplet-race-begins/ https://semiengineering.com/the-chiplet-race-begins/ - a way to integrate dies in a package, where the dies can use specialized processes for different functions - e.g. analog or digital or memory or accelerators or CPUs or networking etc. This would make it easier to iterate memory/CPU/GPU/FPGA/accelerator designs at different rates, and reduce development costs (don't need to support/have IP for every function, just an accelerated set of operations on an optimized process within each chiplet). But it will need progress on inter-chiplet PHY/interface standardization.