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What's the enabling technology behind this? USB4's 40GBit/s is 8x USB3's original 500MBit/s. USB3 was first launched in 2008. Processors have not gotten 8x fast

What's the enabling technology behind this? USB4's 40GBit/s is 8x USB3's original 500MBit/s. USB3 was first launched in 2008. Processors have not gotten 8x faster since 2008, so why haven't these kind of speeds shown up sooner?

marshray 7y ago
Just some theories, but I suspect a lot of the enabling probably came from: A. The work on USB3 to allow more complex negotiation for power, voltage, etc. B. More experience with managing radio frequency interference as USB gets used in the real world. For example: https://www.intel.com/content/www/us/en/products/docs/io/universal-serial-bus/usb3-frequency-interference-paper.html https://www.intel.com/content/www/us/en/products/docs/io/uni... C. 40Gb networking in datacenters. E.g., more chip design teams have confidence building line drivers, receivers, and error recovery circuits to work at these rates. D. Supply. Never underestimate the power of "Well now that we've paid to build the experienced team, what're we doing for 2.0?" E. Demand. A critical mass of consumers have type-C connectors now and are using it for things like docking stations.
sprash 7y ago
The C64 could communicate with peripherals with the same speed as it could talk to RAM. "Technically" this would also be possible on x86_64 machines right from the start. The "enabling technology" in this case is that electrical RX/TX components can be manufactured in smaller feature size without breaking the bank. USB is succesfull because it is cheap.
- erik_seaberg 7y ago
  This. There are already complaints about the cost of USB 3.2 hardware, because measurably charging a hunk of metal gets a lot harder at high frequencies. They had to get more precise and then start borrowing tricks from SATA and PCIe. A 6502 could go up to 3 MHz, but I think the C=64 ran its 6510 near 1 MHz because a clock divider was reserving half the bus cycles for the video chip (no dual-ported VRAM). With dies too small for cache, it didn't make sense to make anything faster than fetching instructions from RAM or ROM. Even the Cray-1 was only able to run at 80 MHz (12.5 ns/cycle) because they paid for four banks of 50 ns RAM. And at those speeds, you could just glue straight wires together into a ribbon cable and call it a day.

marshray 7y ago

Just some theories, but I suspect a lot of the enabling probably came from: A. The work on USB3 to allow more complex negotiation for power, voltage, etc. B. More experience with managing radio frequency interference as USB gets used in the real world. For example: https://www.intel.com/content/www/us/en/products/docs/io/universal-serial-bus/usb3-frequency-interference-paper.html https://www.intel.com/content/www/us/en/products/docs/io/uni... C. 40Gb networking in datacenters. E.g., more chip design teams have confidence building line drivers, receivers, and error recovery circuits to work at these rates. D. Supply. Never underestimate the power of "Well now that we've paid to build the experienced team, what're we doing for 2.0?" E. Demand. A critical mass of consumers have type-C connectors now and are using it for things like docking stations.

sprash 7y ago

The C64 could communicate with peripherals with the same speed as it could talk to RAM. "Technically" this would also be possible on x86_64 machines right from the start. The "enabling technology" in this case is that electrical RX/TX components can be manufactured in smaller feature size without breaking the bank. USB is succesfull because it is cheap.

erik_seaberg 7y ago
This. There are already complaints about the cost of USB 3.2 hardware, because measurably charging a hunk of metal gets a lot harder at high frequencies. They had to get more precise and then start borrowing tricks from SATA and PCIe. A 6502 could go up to 3 MHz, but I think the C=64 ran its 6510 near 1 MHz because a clock divider was reserving half the bus cycles for the video chip (no dual-ported VRAM). With dies too small for cache, it didn't make sense to make anything faster than fetching instructions from RAM or ROM. Even the Cray-1 was only able to run at 80 MHz (12.5 ns/cycle) because they paid for four banks of 50 ns RAM. And at those speeds, you could just glue straight wires together into a ribbon cable and call it a day.