> Both of them mention how Intel is sinking billions of dollars into ASML to try and get this process working, and how impossible everyone thinks it is, so I'm

> Both of them mention how Intel is sinking billions of dollars into ASML to try and get this process working, and how impossible everyone thinks it is, so I'm skeptical that they finally got everything squared away now :) Intel claims EUV is now at production volume and ready for manufacturing introduction on the 7nm node, even at 75-80% EUV machine uptime.[1] At the kind of production volumes Intel is capable of sustaining, and ASML's projected machine throughput, that means they've got more than a dozen of these machines operating in Fab 42 (likely closer to 40-50 if they want to hit a projected 100k wafer starts/month target, with extra machines to make up for the excess downtime; UV litho machines can easily run with 90+% uptime). That should be an enormous win over the current quad patterning they're using at 10nm, cutting out tens of process steps. This stuff is incredibly challenging to get right, but they've been working on it for over a decade and the machines ASML are building now are production machines, not prototypes. And now from the linked article, it seems Trumpf's also made it to production equipment. Once everyone's had more time to operate these machines at scale and really crunch out the bugs, we'll see how far we can continue to push physics on making these tiny etched transistors. 5nm shouldn't be an impossible step with EUV, but the stochastics after that node could make 3nm and smaller logic very questionable. 1: https://www.eetimes.com/document.asp?doc_id=1334769# https://www.eetimes.com/document.asp?doc_id=1334769#