4 ms·

If you're interested in chip fabrication, I heartily recommend watching https://youtu.be/NGFhc8R_uO4 https://youtu.be/NGFhc8R_uO4 - it goes over the evolution o

• deepnotderp 7y ago
  TSMC and Samsung are also exploring EUV, so it's not just Intel. New lithography is necessary to continue shrinking, otherwise mask costs will rise exponentially (literally).
  • tlb 7y ago
    Can you explain the exponential rise in mask costs with shrinking? My naive understanding is that you simply can't resolve features below some fraction of the wavelength. How do more expensive masks get beyond that?
    • blp 7y ago
      I can split any small pitch exposure into separate, larger pitch exposures. For instance, if I need 40nm pitch, and my system is limited to 80nm, I can do 4 exposures. The next shrink requires 8. To figure this out, draw a square, and each node is an exposure. This process works forever in theory, but is limited in practice by the mutual registration of the exposures.
    • testvox 7y ago
      What you can do is basically use partially overlapping beams to energize an area smaller than any of the individual beams (think venn diagram). Its a similar technique (except in 2 dimensions) to radiation therapy where multiple beams of radiation are passed through healthy tissue such that their intersection point is on cancerous tissue. That way only the cancerous tissue receives a highly damaging dose of radiation while the healthy tissue receives significantly lesser dosages.
      • deepnotderp 7y ago
        That doesn't usually work because the the diffraction limit PSF is usually Gaussian and therefore the overlapping region can have lower fluence than the peak regions.
    • deepnotderp 7y ago
      We are not concentrating light below the diffraction limit, instead we are printing features below the diffraction limit with multiple exposures. See here: https://en.m.wikipedia.org/wiki/Multiple_patterning https://en.m.wikipedia.org/wiki/Multiple_patterning Edit: the exponential rise happens because to go 2x smaller I now need to double my # of masks. Of course, in practice overlay accuracy could kill you first.
• LegitShady 7y ago
  I've watched the first one before and enjoyed it, never seen the follow up thanks!
• awalton 7y ago
  > Both of them mention how Intel is sinking billions of dollars into ASML to try and get this process working, and how impossible everyone thinks it is, so I'm skeptical that they finally got everything squared away now :) Intel claims EUV is now at production volume and ready for manufacturing introduction on the 7nm node, even at 75-80% EUV machine uptime.[1] At the kind of production volumes Intel is capable of sustaining, and ASML's projected machine throughput, that means they've got more than a dozen of these machines operating in Fab 42 (likely closer to 40-50 if they want to hit a projected 100k wafer starts/month target, with extra machines to make up for the excess downtime; UV litho machines can easily run with 90+% uptime). That should be an enormous win over the current quad patterning they're using at 10nm, cutting out tens of process steps. This stuff is incredibly challenging to get right, but they've been working on it for over a decade and the machines ASML are building now are production machines, not prototypes. And now from the linked article, it seems Trumpf's also made it to production equipment. Once everyone's had more time to operate these machines at scale and really crunch out the bugs, we'll see how far we can continue to push physics on making these tiny etched transistors. 5nm shouldn't be an impossible step with EUV, but the stochastics after that node could make 3nm and smaller logic very questionable. 1: https://www.eetimes.com/document.asp?doc_id=1334769# https://www.eetimes.com/document.asp?doc_id=1334769#