4 ms·
That's really not a problem just as it's not a problem in normal RAM. With increased speed and endurance it's a doddle to write back a value after reading with
by kirrent 7y ago
That's really not a problem just as it's not a problem in normal RAM. With increased speed and endurance it's a doddle to write back a value after reading with your memory controller even if you're not putting in dedicated refresh hardware. It's really all about density and cost.
- kragen 7y agoUnless you lose power in the interim. Flash doesn't have that problem, and normal RAM has it so badly that we rely on Flash to store permanent data and only use DRAM as an ephemeral cache.
- roca 7y agoSurely you could use a capacitor to buffer enough power to complete the rewrite in the event of an external power failure.
- kirrent 7y agoThe first datasheet I found for a Cypress FRAM chip gives a required power down rate of at most 30us/V which allows it to continue to provide normal operation protecting data. It's a very easy limitation to live with and engineers often deal with far more difficult problems in unexpected power loss than this.
- kragen 7y agoYeah, that doesn't sound that bad. Sounds like the kind of thing that often has subtle bugs in the implementation, though.
- deelowe 7y agoBecause dram loses its memory when powered off not because there's some issue with how refresh works. Needing to refresh memory after a read is hardly any engineering challenge. We've been dealing with it since memory's inception.
- kragen 7y agoRight, obviously.