4 ms·
It's great stuff, but still low capacity and high cost in commercial chips. If you want to play with it, check out TI's MSP430FRxxxx microcontrollers. They have
by leggomylibro 7y ago
It's great stuff, but still low capacity and high cost in commercial chips. If you want to play with it, check out TI's MSP430FRxxxx microcontrollers. They have FRAM instead of Flash.
Also, there are 8-pin FRAM chips with the same pinouts as generic QSPI Flash/RAM/etc chips which you can buy today.
Again, it's still low-density and expensive, but that seems to be improving and it's fun to make applications which can re-write nonvolatile data by word rather than by page.
- baybal2 7y agoAnd destructive reads with limited life cycles, assures a steady recurring revenue for TI...
- jhayward 7y agoTrillions of cycles isn't that "limited", compared to e.g. Flash.
- baybal2 7y agoFRAM is far from trillions of cycles, more close to billions, which still kills it after ~5-7 years of intense use.
- naikrovek 7y agoThat's more than flash. That's more that an SSD, even, probably. If you're writing to flash or FeRAM that much it seems to me that You're Doing It Wrong.
- LocalH 7y agoFlash, I'd agree. But with FeRAM, if you're reading, you're writing either way.
- castratikron 7y agoNo, FRAM really is in the trillions of RW cycles. https://www.cypress.com/file/209146/download https://www.cypress.com/file/209146/download
- baybal2 7y agoTI spec for FRAM is 10^10, but in real life you do feel that it's noticeably lower.
- castratikron 7y agoTI micros are overpriced anyways. The NXP RTs are way better bang for the buck.
- zaarn 7y agoWhat microcontroller will see continued and "Intense" use of it's internal flash? The worst I do to mine is to log sensor data in absence of wifi, that's in the order of bits/minute.
- baybal2 7y agoDue to destructive reads, any XIP read ends up in a write. And the most grievous case is when your function code ends up just few bits longer than cache. That means that those few bytes will get hammered, individually, every cycle. TI's spec for 10^10 endurance is for random writes
- zaarn 7y agoAtleast in the µCs that i used that have flash, program code doesn't sit on the same flash as RAM for these precise reasons. Data flash is separate so this shouldn't be an issue.
- deleted 7y ago[deleted]
- leggomylibro 7y agoWell, if you're really concerned about that, most of them do still have small amounts of SRAM where you can put stuff like commonly-run functions and interrupt handlers.