3 ms·

Von Neumann's popular IAS computer design (ILLIAC, JOHNNIAC, ORACLE, etc.) used an unusual analog adder design. It added two bits and carry-in as analog voltage

by kens 7y ago

Von Neumann's popular IAS computer design (ILLIAC, JOHNNIAC, ORACLE, etc.) used an unusual analog adder design. It added two bits and carry-in as analog voltages, and then converted the resulting voltage to digital sum and carry bits. (Don't confuse this with an analog computer.) This seems convoluted to me, but apparently it was a viable alternative to a normal adder based on Boolean logic. Edit: If you want full details on this adder, pages 60-63 of the manual [1] explains how the adder sums the voltages, getting 54V, 104V, 154V, or 204V from the sum. The digit resolver then turns this voltage into a sum bit. (The carry bit is easier, as it can be generated by a threshold.) You can look at the schematics [2] if you like vacuum tubes; the digit resolver is schematic #200. [1] http://www.bitsavers.org/pdf/univOfIllinoisUrbana/ordvac/ORDVAC_Manual_Volume_1_1952.pdf http://www.bitsavers.org/pdf/univOfIllinoisUrbana/ordvac/ORD... [2] http://www.bitsavers.org/pdf/univOfIllinoisUrbana/ordvac/ORDVAC_Manual_Volume_2_Circuit_and_Logical_Diagrams_1952.pdf http://www.bitsavers.org/pdf/univOfIllinoisUrbana/ordvac/ORD...

kragen 7y ago
It's just surprising they stopped at 3 bits. Weren't those parallel machines? I wonder why they didn't go for 5, 7, or 9. Too many comparators in the ADC? I suppose it was too early to use Gray's 10-bit(?) single-tube ADC—if it ever even saw mass production?
- kens 7y ago
  This took the place of a full adder, which has three input bits. (In other words, it was a single adder with three inputs, not a 3-bit-wide adder.) I don't see how 5 bits would help.
  - kragen 7y ago
    A carry in, two bits from each addend, and three bits out. Halves your carry-chain length in a ripple adder, and the DAC and adder parts of the circuit are a doddle; even an R–2R DAC is plenty, even at many MHz. But then you need a 3-bit ADC for the output. They didn't know about lookahead carry yet, did they? As I said below, the Chinese abacus uses it, but the relevance of that may not have been apparent at the time.

by kens 7y ago

kragen 7y ago

It's just surprising they stopped at 3 bits. Weren't those parallel machines? I wonder why they didn't go for 5, 7, or 9. Too many comparators in the ADC? I suppose it was too early to use Gray's 10-bit(?) single-tube ADC—if it ever even saw mass production?

kens 7y ago
This took the place of a full adder, which has three input bits. (In other words, it was a single adder with three inputs, not a 3-bit-wide adder.) I don't see how 5 bits would help.
- kragen 7y ago
  A carry in, two bits from each addend, and three bits out. Halves your carry-chain length in a ripple adder, and the DAC and adder parts of the circuit are a doddle; even an R–2R DAC is plenty, even at many MHz. But then you need a 3-bit ADC for the output. They didn't know about lookahead carry yet, did they? As I said below, the Chinese abacus uses it, but the relevance of that may not have been apparent at the time.