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> Well . . . and cache coherency issues. But everyone has cache coherency bugs. :-) RISC-V is trying to make that a thing of the past.

• kinghajj 7y ago
  "Can't have cache coherency bugs, if your ISA doesn't require cache coherency!"
  • garmaine 7y ago
    Maybe I need to elaborate. The RISC-V foundation is currently working to strictly define both strong and weak cache coherency modes, and a separate formal verification group is working to define and validate a formal model of cache coherency behavior for the RISC-V ISA. There have been numerous updates on this project at the past couple of RISC-V workshops. When this is all done, ensuring a given implementation is bug-free with respect to cache coherency will be a mechanical process (at least, that is the goal).
    • _chris_ 7y ago
      You are confusing memory consistency with cache coherency.
      • garmaine 7y ago
        On a multi-core system it applies to both.