4 ms·

Datasheets are here: http://dl.sipeed.com/LONGAN/Nano/DOC/ http://dl.sipeed.com/LONGAN/Nano/DOC/ As from my experience with GD's STM32 clones, they did not hav

Datasheets are here: http://dl.sipeed.com/LONGAN/Nano/DOC/ http://dl.sipeed.com/LONGAN/Nano/DOC/ As from my experience with GD's STM32 clones, they did not have a real flash, but copied all your code from SPI-like internal flash to main SRAM on startup. I wonder if they did pull the same stunt with GD32V's EDIT: what is inside stm32 clone: https://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices https://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-... EDIT2: original page now returns 404, it was this board: http://dl.sipeed.com/LONGAN/Nano/Spec/Sipeed%20longan%20nano%20Datasheet%20V1.0.pdf http://dl.sipeed.com/LONGAN/Nano/Spec/Sipeed%20longan%20nano... for $4.90 (https://www.seeedstudio.com/catalogsearch/result/?cat=&q=GD32VF103CBT6 https://www.seeedstudio.com/catalogsearch/result/?cat=&q=GD3...)

kevin_thibedeau 7y ago
Executing from flash is patent encumbered.
- petra 7y ago
  What's novel about that ?
- monocasa 7y ago
  Do what now? People have been executing out of flash for longer than patents are valid.
  - kevin_thibedeau 7y ago
    STM32 has special its ART accelerator cache to prefetch instruction lines from flash and significantly reduce wait states. A clone can't replicate the same performance with a bog standard flash peripheral. https://www.embedded.com/electronics-blogs/break-points/4440388/On-wait-states https://www.embedded.com/electronics-blogs/break-points/4440...
    - monocasa 7y ago
      I know about ART. I actually have some contributions to the STM32F4 reference manual as my team had access to pre production silicon. There's bugs in the prefetching on that thing on early revs and you need to flip a chicken bit. I still don't see anything in there that's not the usual way flash is accessed in cases where it's mapped into the address space for XIP applications. Hell, a lot of the time people will stick something nicer than a dog simple direct mapped cache like ST's implementation.
monocasa 7y ago
It looks like it executes directly out of flash. The instruction bus isn't hooked up to the main AHB matrix, but the instead goes straight into the flash controller. It doesn't look like it even can execute out of SRAM for the same reason. It also looks like you can't DMA from flash to SRAM or peripherals, which isn't the biggest deal, but could have made for some neat efficiencies.
- swetland 7y ago
  The Datasheet has a diagram indicating that but the User Manual claims there's a bus matrix which provide SRAM connectivity from the CPU I/D ports and DMA units. The documentation is... not amazing.

kevin_thibedeau 7y ago

Executing from flash is patent encumbered.

petra 7y ago
What's novel about that ?
monocasa 7y ago
Do what now? People have been executing out of flash for longer than patents are valid.
- kevin_thibedeau 7y ago
  STM32 has special its ART accelerator cache to prefetch instruction lines from flash and significantly reduce wait states. A clone can't replicate the same performance with a bog standard flash peripheral. https://www.embedded.com/electronics-blogs/break-points/4440388/On-wait-states https://www.embedded.com/electronics-blogs/break-points/4440...
  - monocasa 7y ago
    I know about ART. I actually have some contributions to the STM32F4 reference manual as my team had access to pre production silicon. There's bugs in the prefetching on that thing on early revs and you need to flip a chicken bit. I still don't see anything in there that's not the usual way flash is accessed in cases where it's mapped into the address space for XIP applications. Hell, a lot of the time people will stick something nicer than a dog simple direct mapped cache like ST's implementation.

monocasa 7y ago

It looks like it executes directly out of flash. The instruction bus isn't hooked up to the main AHB matrix, but the instead goes straight into the flash controller. It doesn't look like it even can execute out of SRAM for the same reason. It also looks like you can't DMA from flash to SRAM or peripherals, which isn't the biggest deal, but could have made for some neat efficiencies.

swetland 7y ago
The Datasheet has a diagram indicating that but the User Manual claims there's a bus matrix which provide SRAM connectivity from the CPU I/D ports and DMA units. The documentation is... not amazing.