4 ms·

RISC-V is an instruction set - I think you're confusing that particular implementations of RISC-V (of which there are few yet)

bhouston 7y ago
But none of them are competitive at all on an IPC basis right? Don't get me wrong, I would love a RISC-V chip that is competitive with the ARM chips in smartphones but I think we are quite aways away from it for the time being. RISC-V is most successful as microcontrollers who do not have to be state-of-the-art fast, they just have to work reliably.
- kinghajj 7y ago
  BOOM is close to Ivy Bridge IPC in one benchmark. https://people.eecs.berkeley.edu/~celio/ https://people.eecs.berkeley.edu/~celio/
  - atdrummond 7y ago
    Using MHz as a divisor really benefits BOOM and extrapolating from IPC makes some assumptions regarding the future ability of the chip to scale to similar frequencies as Intel's product line. Assuming the best performing BOOM chip refers to the 2018 HotChips tapeout, that chip operated at 1.0 GHz. The lowest speed Ivy Bridge Core/Pentium (a design getting close to a decade old, FWIW) was 2.5 GHz. This means on a core-to-core basis Ivy Bridge is 2.7x more performant. This ignores the benefit of the additional core count of the Core series of Ivy Bridge procs. Today's 9900K is also around 40% more performant than the comparable Ivy Bridge (4960X). That would suggest the performance gains modern Intel design holds over BOOM is closer to 3.8x on a core-to-core basis. Being within an order of magnitude performance-wise is impressive given that BOOM is mainly a one-man show. That said, having about a quarter of Intel's present chips' performance doesn't strike me as particularly "close".
    - kinghajj 7y ago
      IPC means "instructions per cycle," so it's correct to divide the scores by frequency. Totally agree that in total performance, no realized BOOM chip comes close to mainstream Intel chips. I think Chris is working at Esperanto Technologies (https://www.esperanto.ai/technology/); https://www.esperanto.ai/technology/); hopefully, they upstream performance improvements to the BOOM open-source repo.
      - atdrummond 7y ago
        I understand and I appreciate the test from an intellectual standpoint. But the IPC definition is orthogonal to meaningful performance benchmarking when I can't get real world equivalent clock frequencies of each processor type.
        Taniwha 7y ago
        IPC "Instructions per cycle" is also "instructions per clock" - it's right there in the name "per clock" - it's a measure of architectural efficiency independent of clock speed. I agree that being able to build something that runs at speed is equally important but IPC does have an exact meaning
        atdrummond 7y ago
        @Taniwha - I can't reply to you directly because we're so deep, thread-wise. I appreciate and understand the discussion around IPC and how BOOM is a significant improvement on the state of the craft. I cut my early programming teeth by developing PPC and SPARC versions of my business' embedded software products. I'm a longtime fan of alternative architectures and keep up with the industry through attendance at events such as Hot Chips. I am familiar with the terminology here and am not disputing it or the findings of the benchmark. My point was that using IPC in this way obfuscates how far these architectures have yet to go to be competitive in certain markets. Said market competitiveness was the original discussion topic up-thread.
        detaro 7y ago
- lallysingh 7y ago
  If RISC-V takes off, I think we'll first see it come from small shops that put it on the side of a chip with other functionality they're selling. Then it may bubble up into more advanced implementations as demand for the instruction set builds up. Process tech is slowing, so I think that costs of the best processes will go down and we'll see more competition for CPU designs.
- nickik 7y ago
  Look into the Esperanto chips. They will actually over quite high performance soft cores, competing with high level arm.
ummonk 7y ago
No, GP is saying that there is a long way to go before RISC-V implementations can match ARM implementations in competitiveness on an IPC basis.
flmontpetit 7y ago
If you properly examine the context then you can do like most and interpret "ARM" as "current mainstream ARM implementations".

bhouston 7y ago

But none of them are competitive at all on an IPC basis right? Don't get me wrong, I would love a RISC-V chip that is competitive with the ARM chips in smartphones but I think we are quite aways away from it for the time being. RISC-V is most successful as microcontrollers who do not have to be state-of-the-art fast, they just have to work reliably.

kinghajj 7y ago
BOOM is close to Ivy Bridge IPC in one benchmark. https://people.eecs.berkeley.edu/~celio/ https://people.eecs.berkeley.edu/~celio/
- atdrummond 7y ago
  Using MHz as a divisor really benefits BOOM and extrapolating from IPC makes some assumptions regarding the future ability of the chip to scale to similar frequencies as Intel's product line. Assuming the best performing BOOM chip refers to the 2018 HotChips tapeout, that chip operated at 1.0 GHz. The lowest speed Ivy Bridge Core/Pentium (a design getting close to a decade old, FWIW) was 2.5 GHz. This means on a core-to-core basis Ivy Bridge is 2.7x more performant. This ignores the benefit of the additional core count of the Core series of Ivy Bridge procs. Today's 9900K is also around 40% more performant than the comparable Ivy Bridge (4960X). That would suggest the performance gains modern Intel design holds over BOOM is closer to 3.8x on a core-to-core basis. Being within an order of magnitude performance-wise is impressive given that BOOM is mainly a one-man show. That said, having about a quarter of Intel's present chips' performance doesn't strike me as particularly "close".
  - kinghajj 7y ago
    IPC means "instructions per cycle," so it's correct to divide the scores by frequency. Totally agree that in total performance, no realized BOOM chip comes close to mainstream Intel chips. I think Chris is working at Esperanto Technologies (https://www.esperanto.ai/technology/); https://www.esperanto.ai/technology/); hopefully, they upstream performance improvements to the BOOM open-source repo.
    - atdrummond 7y ago
      I understand and I appreciate the test from an intellectual standpoint. But the IPC definition is orthogonal to meaningful performance benchmarking when I can't get real world equivalent clock frequencies of each processor type.
      - Taniwha 7y ago
        IPC "Instructions per cycle" is also "instructions per clock" - it's right there in the name "per clock" - it's a measure of architectural efficiency independent of clock speed. I agree that being able to build something that runs at speed is equally important but IPC does have an exact meaning
      - atdrummond 7y ago
        @Taniwha - I can't reply to you directly because we're so deep, thread-wise. I appreciate and understand the discussion around IPC and how BOOM is a significant improvement on the state of the craft. I cut my early programming teeth by developing PPC and SPARC versions of my business' embedded software products. I'm a longtime fan of alternative architectures and keep up with the industry through attendance at events such as Hot Chips. I am familiar with the terminology here and am not disputing it or the findings of the benchmark. My point was that using IPC in this way obfuscates how far these architectures have yet to go to be competitive in certain markets. Said market competitiveness was the original discussion topic up-thread.
        detaro 7y ago
lallysingh 7y ago
If RISC-V takes off, I think we'll first see it come from small shops that put it on the side of a chip with other functionality they're selling. Then it may bubble up into more advanced implementations as demand for the instruction set builds up. Process tech is slowing, so I think that costs of the best processes will go down and we'll see more competition for CPU designs.
nickik 7y ago
Look into the Esperanto chips. They will actually over quite high performance soft cores, competing with high level arm.

ummonk 7y ago

No, GP is saying that there is a long way to go before RISC-V implementations can match ARM implementations in competitiveness on an IPC basis.

flmontpetit 7y ago

If you properly examine the context then you can do like most and interpret "ARM" as "current mainstream ARM implementations".