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What's being released here is the instruction set architecture, not the microarchitecture for any particular processor design. As RISC ISAs go Power is relativ
by Symmetry 7y ago
What's being released here is the instruction set architecture, not the microarchitecture for any particular processor design. As RISC ISAs go Power is relatively pragmatic, though not to the extent 32 bit ARM is, so it has relatively good code density compared to SPARC and MIPS. Plus it doesn't have annoying misfeatures like branch delay slots or register windows.
For mobile processors it seems about as good as 64 bit ARM but with a bit less software support in the mobile world, though a good history of software support in general.
- tpearson-raptor 7y agoAn interesting offset for the latter is that you could develop your software on a high end system that matches the mobile architecture. Anyone who has has to fight with (/slow/) pure emulation of e.g. Android on ARM knows the pain this causes, multiplied by the thousands of developers. That's a lot of wasted man hours vs. the develop on same architecture model.