New improvements(zeno semi) do talk about 1T sram, and dram chiplet solution will have the same limits in memory size as wafer-scale, So maybe the sram vs dram

New improvements(zeno semi) do talk about 1T sram, and dram chiplet solution will have the same limits in memory size as wafer-scale, So maybe the sram vs dram gap will be close enough? And as for IO, maybe it's possible(thermally) to assemble this on an IO interposer ?