First: thanks, this was exactly the kind of historic knowledge I hoped would show up in this thread! Gene Amdahl ran this; geeze, no surprise they got funded.

First: thanks, this was exactly the kind of historic knowledge I hoped would show up in this thread! Gene Amdahl ran this; geeze, no surprise they got funded. Do you happen to know how many "compute units" this chip was designed to handle? https://en.m.wikipedia.org/wiki/Trilogy_Systems https://en.m.wikipedia.org/wiki/Trilogy_Systems > These techniques included wafer scale integration (WSI), with the goal of producing a computer chip that was 2.5 inch on one side. At the time, computer chips of only 0.25 inch on a side could be reliably manufactured. This giant chip was to be connected to the rest of the system using a package with 1200 pins, an enormous number at the time. Previously, mainframe computers were built from hundreds of computer chips due to the size of standard computer chips. These computer systems were hampered through chip-to-chip communication which both slowed down performance as well consumed much power. > As with other WSI projects, Trilogy's chip design relied on redundancy, that is replication of functional units, to overcome the manufacturing defects that precluded such large chips. If one functional unit was not fabricated properly, it would be switched out through on-chip wiring and another correctly functioning copy would be used. By keeping most communication on-chip, the dual benefits of higher performance and lower power consumption were supposed to be achieved. Lower power consumption meant less expensive cooling systems, which would aid in lower system costs. Edit: '"Triple Modular Redundancy" was employed systematically. Every logic gate and every flip-flop were triplicated with binary two-out-of-three voting at each flip-flop.' This seems like it should it should complicate things quite a bit more dramatically.. they were doing redundancy at a gate-level, rather than a a CPU-core level.