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> The 46,225 square millimeters of silicon in the Cerebras WSE house 400,000 AI-optimized, no-cache, no-overhead, compute cores > But Cerebras has designed its

> The 46,225 square millimeters of silicon in the Cerebras WSE house 400,000 AI-optimized, no-cache, no-overhead, compute cores > But Cerebras has designed its chip to be redundant, so one impurity won’t disable the whole chip. This sounds kinda clever to a semi-layperson. Has this been attempted before? Edit: at this scale. Not single-digit cores CPUs being binned, but 100k+ CPU core chips with some kind of automated core-deactivation on failure.

rrss 7y ago
Yes, every chip of moderate size does this. Selling floorswept chips as lower performance SKUs is very common.
- groundlogic 7y ago
  Sure, that practice is pretty wellknown. But at this scale?
  - deleted 7y ago
    [deleted]
vardump 7y ago
>> But Cerebras has designed its chip to be redundant, so one impurity won’t disable the whole chip. > This sounds kinda clever to a semi-layperson. Has this been attempted before? I think every large chip is like that nowadays. It's just a matter of degree.
robin_reala 7y ago
Yep, it’s standard practice. The old AMD tri-core chips for example were all physically four cores with a (usually) broken one disabled. Modern AMD chips use multiple chiplets on a single board to extend yields.
- happycube 7y ago
  ... and some of the new Epyc chips use only two cores per die out of eight. Customers still come out ahead since those chips have far more cache than a chip with 2 fully enabled 8 core dies.
MisterTea 7y ago
Remember three core AMD chips? They were quad core chips where one core was non functional or didn't meet spec. They simply disable the bad core and sell it as a three core. Though it didn't do well as who wants to buy a "broken" quad core?
- opencl 7y ago
  This is how most large-ish chips are sold. AMD no longer sells 3 core CPUs but they sell 6 and 4 core models which are partially disabled 8 core dies. The 6 core even seems to be their best selling model because it has a very good price:performance ratio. The Radeon 5700 is a cut down 5700XT, RTX 2060 is a cut down 2070, etc.
rwmj 7y ago
Every time you see a CPU with 8 cores and one next to it with 6 cores at a lower price, they are generally the same chip but the 6 core one had 2 faulty cores which were disabled at the fab. The reason for the price difference is that chips with all good cores happen infrequently. Designing wafer-level integration is not new either. It was in fact very fashionable in the 80s (although not very successful): https://en.wikipedia.org/wiki/Wafer-scale_integration https://en.wikipedia.org/wiki/Wafer-scale_integration
baybal2 7y ago
> This sounds kinda clever to a semi-layperson. Has this been attempted before? Yes, by Trilogy Systems, and it went bust spectacularly. It raised +200m plus of capital (back in seventies!) and turned out to be the biggest financial failure in Silicon Valley's history. https://en.m.wikipedia.org/wiki/Trilogy_Systems https://en.m.wikipedia.org/wiki/Trilogy_Systems
- groundlogic 7y ago
  First: thanks, this was exactly the kind of historic knowledge I hoped would show up in this thread! Gene Amdahl ran this; geeze, no surprise they got funded. Do you happen to know how many "compute units" this chip was designed to handle? https://en.m.wikipedia.org/wiki/Trilogy_Systems https://en.m.wikipedia.org/wiki/Trilogy_Systems > These techniques included wafer scale integration (WSI), with the goal of producing a computer chip that was 2.5 inch on one side. At the time, computer chips of only 0.25 inch on a side could be reliably manufactured. This giant chip was to be connected to the rest of the system using a package with 1200 pins, an enormous number at the time. Previously, mainframe computers were built from hundreds of computer chips due to the size of standard computer chips. These computer systems were hampered through chip-to-chip communication which both slowed down performance as well consumed much power. > As with other WSI projects, Trilogy's chip design relied on redundancy, that is replication of functional units, to overcome the manufacturing defects that precluded such large chips. If one functional unit was not fabricated properly, it would be switched out through on-chip wiring and another correctly functioning copy would be used. By keeping most communication on-chip, the dual benefits of higher performance and lower power consumption were supposed to be achieved. Lower power consumption meant less expensive cooling systems, which would aid in lower system costs. Edit: '"Triple Modular Redundancy" was employed systematically. Every logic gate and every flip-flop were triplicated with binary two-out-of-three voting at each flip-flop.' This seems like it should it should complicate things quite a bit more dramatically.. they were doing redundancy at a gate-level, rather than a a CPU-core level.
ryacko 7y ago
It just has to detect damage and route around it. It is just an orchestration scheme in miniature. Relevant XKCD: https://xkcd.com/1737/ https://xkcd.com/1737/

rrss 7y ago

Yes, every chip of moderate size does this. Selling floorswept chips as lower performance SKUs is very common.

groundlogic 7y ago
Sure, that practice is pretty wellknown. But at this scale?
- deleted 7y ago
  [deleted]

vardump 7y ago

>> But Cerebras has designed its chip to be redundant, so one impurity won’t disable the whole chip. > This sounds kinda clever to a semi-layperson. Has this been attempted before? I think every large chip is like that nowadays. It's just a matter of degree.

robin_reala 7y ago

Yep, it’s standard practice. The old AMD tri-core chips for example were all physically four cores with a (usually) broken one disabled. Modern AMD chips use multiple chiplets on a single board to extend yields.

happycube 7y ago
... and some of the new Epyc chips use only two cores per die out of eight. Customers still come out ahead since those chips have far more cache than a chip with 2 fully enabled 8 core dies.

MisterTea 7y ago

Remember three core AMD chips? They were quad core chips where one core was non functional or didn't meet spec. They simply disable the bad core and sell it as a three core. Though it didn't do well as who wants to buy a "broken" quad core?

opencl 7y ago
This is how most large-ish chips are sold. AMD no longer sells 3 core CPUs but they sell 6 and 4 core models which are partially disabled 8 core dies. The 6 core even seems to be their best selling model because it has a very good price:performance ratio. The Radeon 5700 is a cut down 5700XT, RTX 2060 is a cut down 2070, etc.

rwmj 7y ago

Every time you see a CPU with 8 cores and one next to it with 6 cores at a lower price, they are generally the same chip but the 6 core one had 2 faulty cores which were disabled at the fab. The reason for the price difference is that chips with all good cores happen infrequently. Designing wafer-level integration is not new either. It was in fact very fashionable in the 80s (although not very successful): https://en.wikipedia.org/wiki/Wafer-scale_integration https://en.wikipedia.org/wiki/Wafer-scale_integration

baybal2 7y ago

> This sounds kinda clever to a semi-layperson. Has this been attempted before? Yes, by Trilogy Systems, and it went bust spectacularly. It raised +200m plus of capital (back in seventies!) and turned out to be the biggest financial failure in Silicon Valley's history. https://en.m.wikipedia.org/wiki/Trilogy_Systems https://en.m.wikipedia.org/wiki/Trilogy_Systems

groundlogic 7y ago
First: thanks, this was exactly the kind of historic knowledge I hoped would show up in this thread! Gene Amdahl ran this; geeze, no surprise they got funded. Do you happen to know how many "compute units" this chip was designed to handle? https://en.m.wikipedia.org/wiki/Trilogy_Systems https://en.m.wikipedia.org/wiki/Trilogy_Systems > These techniques included wafer scale integration (WSI), with the goal of producing a computer chip that was 2.5 inch on one side. At the time, computer chips of only 0.25 inch on a side could be reliably manufactured. This giant chip was to be connected to the rest of the system using a package with 1200 pins, an enormous number at the time. Previously, mainframe computers were built from hundreds of computer chips due to the size of standard computer chips. These computer systems were hampered through chip-to-chip communication which both slowed down performance as well consumed much power. > As with other WSI projects, Trilogy's chip design relied on redundancy, that is replication of functional units, to overcome the manufacturing defects that precluded such large chips. If one functional unit was not fabricated properly, it would be switched out through on-chip wiring and another correctly functioning copy would be used. By keeping most communication on-chip, the dual benefits of higher performance and lower power consumption were supposed to be achieved. Lower power consumption meant less expensive cooling systems, which would aid in lower system costs. Edit: '"Triple Modular Redundancy" was employed systematically. Every logic gate and every flip-flop were triplicated with binary two-out-of-three voting at each flip-flop.' This seems like it should it should complicate things quite a bit more dramatically.. they were doing redundancy at a gate-level, rather than a a CPU-core level.

ryacko 7y ago

It just has to detect damage and route around it. It is just an orchestration scheme in miniature. Relevant XKCD: https://xkcd.com/1737/ https://xkcd.com/1737/