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> Every documentation I've seen is quite light on the branch prediction improvements. In one of the pictures in the article, it says the new architecture uses
by piadodjanho 7y ago
> Every documentation I've seen is quite light on the branch prediction improvements.
In one of the pictures in the article, it says the new architecture uses the TAGE Branche predictor. This is likely based on the work of Andre Seznec. There are many articles on the implementation (but they can be difficult to understand if you are not already familiar with his work).
I've implemented the bare bone predictor on a computer architecture course, you can see an abridged version of my presentation slides here[1]. Note this only describes the bare bone predictor, in recent work Andre Senzec added a Loop predictor and a Statistical Correlation Unit to increase the accuracy.
There are some work using TAGE with perceptions in the Statistical Correlation unit.
[1] https://docs.google.com/presentation/d/1aUrwD-ENYPB7pMrCoYmEcLamuwyk_WfrggBT_3vOZBs/edit?usp=sharing https://docs.google.com/presentation/d/1aUrwD-ENYPB7pMrCoYmE...
- MayeulC 7y agoThank you, I hadn't realized those branch predictors were actually documented, and thought that they were referring to internal names. It is nice to see research being applied to new mainstream chips relatively quickly. In complement to your slides, there is a short overview here [1] (this is actually the first search result).
- MayeulC 7y agoI forgot to put the link. One of the first search results. [1]: https://comparch.net/2013/06/30/why-tage-is-the-best/ https://comparch.net/2013/06/30/why-tage-is-the-best/