4 ms·
> “We like features that improve both power and performance,” Clark elaborated. “Being on the right path more often is important because the worst use of power
by MayeulC 7y ago
> “We like features that improve both power and performance,” Clark elaborated. “Being on the right path more often is important because the worst use of power is executing instructions that you are just going to throw away. We are not throwing work away after we figure out dynamically that we were wrong to do it. This definitely burns more power on the front end, but it pays dividends on the back end.”
Every documentation I've seen is quite light on the branch prediction improvements. Going by the slides, they improved is accuracy by 1/3; I'd be curious to know how.
Side note: if your superscalar is big enough (yeah, those registers use power), couldn't you just get rid of branch prediction at no performance cost (doing something else while waiting for the data)?
My only grudge against Zen (as a consumer) is that the AM4 socket is intended for both APUs and CPUs. While this is a good thing, I have a couple utterly useless video outputs on my motherboard. I would have liked AMD to include some display driver circuitry on every chip. Maybe in the I/O die, if they use such a thing in all of their designs going forward? I mean, I would be quite content with using software rendering when I need to drive a screen, or even spare a bit of memory bandwidth and CPU cycles to drive an extra display from my desktop's graphics card.
- piadodjanho 7y ago> Every documentation I've seen is quite light on the branch prediction improvements. In one of the pictures in the article, it says the new architecture uses the TAGE Branche predictor. This is likely based on the work of Andre Seznec. There are many articles on the implementation (but they can be difficult to understand if you are not already familiar with his work). I've implemented the bare bone predictor on a computer architecture course, you can see an abridged version of my presentation slides here[1]. Note this only describes the bare bone predictor, in recent work Andre Senzec added a Loop predictor and a Statistical Correlation Unit to increase the accuracy. There are some work using TAGE with perceptions in the Statistical Correlation unit. [1] https://docs.google.com/presentation/d/1aUrwD-ENYPB7pMrCoYmEcLamuwyk_WfrggBT_3vOZBs/edit?usp=sharing https://docs.google.com/presentation/d/1aUrwD-ENYPB7pMrCoYmE...
- MayeulC 7y agoThank you, I hadn't realized those branch predictors were actually documented, and thought that they were referring to internal names. It is nice to see research being applied to new mainstream chips relatively quickly. In complement to your slides, there is a short overview here [1] (this is actually the first search result).
- MayeulC 7y agoI forgot to put the link. One of the first search results. [1]: https://comparch.net/2013/06/30/why-tage-is-the-best/ https://comparch.net/2013/06/30/why-tage-is-the-best/