There was a publication in IEEE COOL Chips 21 (2018) [978-1-5386-6103-1/18] which compared a closed source implementation by a company (whose founder was involv

There was a publication in IEEE COOL Chips 21 (2018) [978-1-5386-6103-1/18] which compared a closed source implementation by a company (whose founder was involved in the creation of SuperH i think) of SH2 with RISC-V and an historic (pirate (as in patents were not expired then)) implementation of SH2 called Aquarius by some hobbyist. The comparison seems to have some methodological flaws. But one result is, that is unaffected by them in my opinion is "that 2 stage SH2 re-implementation" needs fewer FPGA resources than "that 2 stage RISC-V re-implementation" on the same hardware at the same clock. That honestly does not say much but it is the best comparison i am aware of.