Neat, but it looks like this hasn't been in development since 2016. I would think it's probably best to use a RISC-V design if you want an open RISC CPU core to

Neat, but it looks like this hasn't been in development since 2016. I would think it's probably best to use a RISC-V design if you want an open RISC CPU core to put on an FPGA. You'll get better compiler and tool support, and probably a wider variety of available designs.