3 ms·
That was true before Skylake, but is no longer true since they moved away from the multi ring architecture.
by shaklee3 7y ago
That was true before Skylake, but is no longer true since they moved away from the multi ring architecture.
- jdsully 7y agoEven with the mesh the number of hops is variable based on which core is requesting and the physical geometry of the chip. The cores right beside the IMC will have the lowest latency. See this diagram: https://en.wikichip.org/wiki/intel/mesh_interconnect_architecture https://en.wikichip.org/wiki/intel/mesh_interconnect_archite... The main improvement is the max number of hops is log(n) instead N/2.