3 ms·
The TLB bug (Errata 298, doc 41322 if you really care - while the processor was attempting to set the A/D bits in a page table entry, an L2->L3 eviction of that
by vsrinivas 7y ago
The TLB bug (Errata 298, doc 41322 if you really care - while the processor was attempting to set the A/D bits in a page table entry, an L2->L3 eviction of that PTE could occur) was one of a great many things wrong with that chip.
* A number of errata (not just 298) delayed full production, sapped performance, or negatively impacted idle power. Take a look at doc 41322, DR-BA step for many samples.
* It was late and didn't achieve performance targets; it missed clock rate targets and 2 MiB L3 was insufficient.
* Intel delivered a very compelling server part (Nehalem) during the lifecycle of family 10h.