4 ms·

Silly question (not much low level knowledge): which is the architecture that is today "virtually the same" for all CPUs?

dragontamer 7y ago
I don't think there's a simple name for the modern architecture. Instead, I listed the major features off individually: > Out-of-Order, deeply pipelined, branch-predicted SIMD-accelerated load/store architectures with hidden reordering registers and multiple execution ports with 64-byte coherent caches implementing MESI-based messaging targeting Acquire/Release semantics over SMT Multithreading. In short: Intel Skylake: https://en.wikichip.org/w/images/e/ee/skylake_server_block_diagram.svg https://en.wikichip.org/w/images/e/ee/skylake_server_block_d... Which is pretty darn similar to say: https://en.wikichip.org/w/images/5/57/cortex-a76_block_diagram.svg https://en.wikichip.org/w/images/5/57/cortex-a76_block_diagr... Arm Cortex-A76 is smaller because its designed for cellphones. But you can see how the overall CPU design principles are nearly identical to what Intel Skylake is doing. There was a time when ARM and Intel CPUs were extremely different: thus the RISC vs CISC debate. But its not the 90s anymore: today's architectures are extremely similar. A lot of these features are being shared between all designs today. The hard part is that some of these concepts are RISC (out-of-order, load/store, and deep pipelines). Some are CISC (SIMD-instructions and other hardware acceleration instructions, like hardware level AES or RDRAND instructions). Some are hybrids. RISC chips were traditionally multithreaded with relaxed atomics or maybe consume-release semantics. CISC chips were strongly ordered. Acquire-release semantics meets in the middle: stronger than consume-release, weaker than strongly ordered. Finally, some tidbits are just happy accidents. DDR4, LPDDR4, GDDR5, GDDR6, HBM, and HBM2 RAM all work on 64-byte chunks (typically burst-length 8). So all modern chips work on 64-byte transactions with RAM. Neither a CISC nor RISC concept, its just everybody cooperating with the same cache-line size due to how memory works today. --------- If you want to call it a "RISCy-CISC" or a "CISCy-RISC", maybe that will work. Modern architecture is a hybrid of concepts, taking the best (or blending the best features) from previous debates in history. The important parts of history, is the discussion. The realization for why certain features were good or bad. The deep-dive nature of these old USENET posts archive the discussion excellently. Its a great snapshot into the thinking in 1993.
- mikorym 7y ago
  Thanks for this reply. The next question I guess is whether we do this because of experience or because of debate? Your examples of CISC instructions are specialised, as one would expect, so maybe the earlier generations of engineers simply expected more specialised machines? Ironically perhaps, with the bitcoin era, there is now more interest in specialised machines again, though my impression is hardware manifacturers are more focused on practicality. Maybe people have realised the benefit of a general CISCy-RISC architechture for the sake of not wasting time with debate?
  - dragontamer 7y ago
    CPU Engineers always designed for the needs of their customers: with early computers having much better support for decimal arithmetic (which was popular in the 60s through 80s, but less popular today). Overall, today's high-performance CPU programmers (and their tools: particularly their compilers) have a set of expectations, and CPU Engineers are designing their computers with those expectations in mind. That's really all there is too it.

dragontamer 7y ago

I don't think there's a simple name for the modern architecture. Instead, I listed the major features off individually: > Out-of-Order, deeply pipelined, branch-predicted SIMD-accelerated load/store architectures with hidden reordering registers and multiple execution ports with 64-byte coherent caches implementing MESI-based messaging targeting Acquire/Release semantics over SMT Multithreading. In short: Intel Skylake: https://en.wikichip.org/w/images/e/ee/skylake_server_block_diagram.svg https://en.wikichip.org/w/images/e/ee/skylake_server_block_d... Which is pretty darn similar to say: https://en.wikichip.org/w/images/5/57/cortex-a76_block_diagram.svg https://en.wikichip.org/w/images/5/57/cortex-a76_block_diagr... Arm Cortex-A76 is smaller because its designed for cellphones. But you can see how the overall CPU design principles are nearly identical to what Intel Skylake is doing. There was a time when ARM and Intel CPUs were extremely different: thus the RISC vs CISC debate. But its not the 90s anymore: today's architectures are extremely similar. A lot of these features are being shared between all designs today. The hard part is that some of these concepts are RISC (out-of-order, load/store, and deep pipelines). Some are CISC (SIMD-instructions and other hardware acceleration instructions, like hardware level AES or RDRAND instructions). Some are hybrids. RISC chips were traditionally multithreaded with relaxed atomics or maybe consume-release semantics. CISC chips were strongly ordered. Acquire-release semantics meets in the middle: stronger than consume-release, weaker than strongly ordered. Finally, some tidbits are just happy accidents. DDR4, LPDDR4, GDDR5, GDDR6, HBM, and HBM2 RAM all work on 64-byte chunks (typically burst-length 8). So all modern chips work on 64-byte transactions with RAM. Neither a CISC nor RISC concept, its just everybody cooperating with the same cache-line size due to how memory works today. --------- If you want to call it a "RISCy-CISC" or a "CISCy-RISC", maybe that will work. Modern architecture is a hybrid of concepts, taking the best (or blending the best features) from previous debates in history. The important parts of history, is the discussion. The realization for why certain features were good or bad. The deep-dive nature of these old USENET posts archive the discussion excellently. Its a great snapshot into the thinking in 1993.

mikorym 7y ago
Thanks for this reply. The next question I guess is whether we do this because of experience or because of debate? Your examples of CISC instructions are specialised, as one would expect, so maybe the earlier generations of engineers simply expected more specialised machines? Ironically perhaps, with the bitcoin era, there is now more interest in specialised machines again, though my impression is hardware manifacturers are more focused on practicality. Maybe people have realised the benefit of a general CISCy-RISC architechture for the sake of not wasting time with debate?
- dragontamer 7y ago
  CPU Engineers always designed for the needs of their customers: with early computers having much better support for decimal arithmetic (which was popular in the 60s through 80s, but less popular today). Overall, today's high-performance CPU programmers (and their tools: particularly their compilers) have a set of expectations, and CPU Engineers are designing their computers with those expectations in mind. That's really all there is too it.